2010 IEEE/ACM International Symposium on Nanoscale Architectures最新文献

Fault modeling for FinFET circuits FinFET电路的故障建模

2010 IEEE/ACM International Symposium on Nanoscale Architectures Pub Date : 2010-06-17 DOI: 10.1109/NANOARCH.2010.5510927

M. O. Simsir, A. Bhoj, N. Jha

引用次数: 44

Compact method for modeling and simulation of memristor devices: Ion conductor chalcogenide-based memristor devices 忆阻器器件建模与仿真的紧凑方法:离子导体硫化物基忆阻器器件

2010 IEEE/ACM International Symposium on Nanoscale Architectures Pub Date : 2010-06-17 DOI: 10.1109/NANOARCH.2010.5510936

R. Pino, James W. Bohl, N. McDonald, B. Wysocki, Peter J. Rozwood, K. Campbell, A. Oblea, Achyut Timilsina

引用次数: 82

Towards logic functions as the device 向着逻辑功能作为器件

2010 IEEE/ACM International Symposium on Nanoscale Architectures Pub Date : 2010-06-17 DOI: 10.1109/NANOARCH.2010.5510934

Prasad Shabadi, A. Khitun, P. Narayanan, M. Bao, I. Koren, Kang L. Wang, C. A. Moritz

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引用次数: 27

Reducing transistor count in clocked standard cells with ambipolar double-gate FETs 用双极双栅fet减少时钟标准单元的晶体管计数

2010 IEEE/ACM International Symposium on Nanoscale Architectures Pub Date : 2010-06-17 DOI: 10.1109/NANOARCH.2010.5510928

K. Jabeur, D. Navarro, I. O’Connor, P. Gaillardon, M. B. Jamaa, F. Clermidy

引用次数: 13

Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes 金属管存在下碳纳米管电路的设计方法

2010 IEEE/ACM International Symposium on Nanoscale Architectures Pub Date : 2010-06-17 DOI: 10.1109/NANOARCH.2010.5510924

R. Ashraf, Rajeev K. Nain, M. Chrzanowska-Jeske, S. Narendra

{"title":"Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes","authors":"R. Ashraf, Rajeev K. Nain, M. Chrzanowska-Jeske, S. Narendra","doi":"10.1109/NANOARCH.2010.5510924","DOIUrl":"https://doi.org/10.1109/NANOARCH.2010.5510924","url":null,"abstract":"Carbon Nanotube Field Effect Transistor (CNFET) has a potential to become successor of Si-CMOS devices because of its excellent electronic properties. One of the most important challenges for the CNT-based technology is the undesired presence of metallic tubes which adversely impacts the performance, power and yield of CNT based circuits. Different tube configurations in CNFET transistor like Parallel Tube (PT) and Transistor Stacking (TrS) can be used to trade-off yield for performance. The Monte Carlo (MC) simulations of a full adder show that TrS implementation along with parallelism in the critical path can result in the same performance as the PT implementation (demonstrated significant improvements over CMOS) but with 4X increased functional yield and 6X reduced static power. Furthermore, we proposed architecture based on regular logic bricks that are designed using different tube configurations. Monte Carlo simulations show that for 10% metallic tubes logic bricks implemented with hybrid configurations of CNFETs can help to reduce the performance impact by 2X as compared to homogeneous bricks implemented with only TrS CNFETs. In comparison to homogeneous bricks realized with only PT CNFETs, the static power can be reduced by 2X and yield can be increased from 22% to 54%.","PeriodicalId":306717,"journal":{"name":"2010 IEEE/ACM International Symposium on Nanoscale Architectures","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122305614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

High throughput and low power dissipation in QCA pipelines using Bennett clocking 采用班尼特时钟的QCA管道高吞吐量和低功耗

2010 IEEE/ACM International Symposium on Nanoscale Architectures Pub Date : 2010-06-17 DOI: 10.1109/NANOARCH.2010.5510931

M. Ottavi, S. Pontarelli, E. Debenedictis, A. Salsano, P. Kogge, F. Lombardi

引用次数: 9

Stochastic nanoscale addressing for logic 用于逻辑的随机纳米级寻址

2010 IEEE/ACM International Symposium on Nanoscale Architectures Pub Date : 2010-06-17 DOI: 10.1109/NANOARCH.2010.5510926

Eric Rachlin, J. Savage

引用次数: 0

Design and comparison of NML systolic architectures NML收缩结构的设计与比较

2010 IEEE/ACM International Symposium on Nanoscale Architectures Pub Date : 2010-06-17 DOI: 10.1109/NANOARCH.2010.5510929

M. Crocker, X. Hu, M. Niemier

引用次数: 25

NanoV: Nanowire-based VLSI design NanoV:基于纳米线的VLSI设计

2010 IEEE/ACM International Symposium on Nanoscale Architectures Pub Date : 2010-06-17 DOI: 10.1109/NANOARCH.2010.5510925

M. O. Simsir, N. Jha

引用次数: 0

Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications 用于FPGA和结构化ASIC应用的双极性cntfet的常规结构设计

2010 IEEE/ACM International Symposium on Nanoscale Architectures Pub Date : 2010-06-17 DOI: 10.1109/NANOARCH.2010.5510923

M. D. Marchi

引用次数: 13