Bao Liu, Zhen Cao, Jun Tao, Xuan Zeng, Pushan Tang, H. P. Wong
{"title":"Intel LVS logic as a combinational logic paradigm in CNT technology","authors":"Bao Liu, Zhen Cao, Jun Tao, Xuan Zeng, Pushan Tang, H. P. Wong","doi":"10.1109/NANOARCH.2010.5510922","DOIUrl":"https://doi.org/10.1109/NANOARCH.2010.5510922","url":null,"abstract":"In this paper, we systematically evaluate combinational logic families for CNT technology implementation for a variety of logic families, signal transition times, and transistor parameters. We compare CMOS static logic, transmission gate logic, and Intel LVS logic in CNT and silicon technologies by SPICE simulation based on Predictive Technology Model and Stanford compact CNFET models. We observe that CMOS static logic in CNT technology achieves limited (e.g., 3.44×) performance improvement and (e.g., 3.83×) power consumption reduction, while transmission gate logic and Intel LVS logic achieves more significant performance improvement and orders-of-magnitude of power consumption reduction. Intel LVS logic achieves an average of 4.02× performance improvement and 1137.64× power consumption reduction compared with CMOS static logic in silicon for the same combinational logic functions and input signals, and enhanced reliability, making it an ideal combinational logic circuit paradigm in CNT technology.","PeriodicalId":306717,"journal":{"name":"2010 IEEE/ACM International Symposium on Nanoscale Architectures","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130614103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jeyavijayan Rajendran, H. Manem, R. Karri, G. Rose
{"title":"Memristor based programmable threshold logic array","authors":"Jeyavijayan Rajendran, H. Manem, R. Karri, G. Rose","doi":"10.1109/NANOARCH.2010.5510933","DOIUrl":"https://doi.org/10.1109/NANOARCH.2010.5510933","url":null,"abstract":"In this work, we utilized memristors in the realization of power and area efficient programmable threshold gates. Memristors are used as weights at the inputs of the threshold gates. The threshold gates are programmed by changing the memristance to enable implementation of different Boolean functions. A new threshold gate-array architecture is proposed and evaluated for power, area and delay metrics. The CAD setup that was utilized in the evaluation of the aforementioned architecture, can also be used to analyse the performance of emerging computing technologies. The proposed architecture achieves an average power reduction of 75% and area (transistor count) reduction of 75% when compared to look-up-table (LUT) based logic with some delay penalty.","PeriodicalId":306717,"journal":{"name":"2010 IEEE/ACM International Symposium on Nanoscale Architectures","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134364827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaowen Wu, Yaoyao Ye, Wei Zhang, Weichen Liu, M. Nikdast, Xuan Wang, Jiang Xu
{"title":"UNION: A unified inter/intra-chip optical network for chip multiprocessors","authors":"Xiaowen Wu, Yaoyao Ye, Wei Zhang, Weichen Liu, M. Nikdast, Xuan Wang, Jiang Xu","doi":"10.1109/NANOARCH.2010.5510930","DOIUrl":"https://doi.org/10.1109/NANOARCH.2010.5510930","url":null,"abstract":"As modern computing systems become increasingly complex, communication efficiency among and inside chips has become as important as the computation speeds of individual processor cores. Traditionally, inter-chip and intra-chip communication architectures are separately designed to maximize design flexibility under different constraints. However, jointly designing communication architectures for both inter-chip and intra-chip communication could potentially yield better solutions. In this paper, we present a unified inter/intra-chip optical network, called UNION, for chip multiprocessors (CMP). UNION is based on recent progress in nano-photonic technologies. It connects not only processors on a single CMP but also multiple CMPs in a system. UNION employs a hierarchical optical network to separate inter-chip communication traffic from intra-chip communication traffic. It fully utilizes a single optical network to transmit both payload packets and control packets. The network controller on each CMP not only manages intra-chip communications but also collaborate with each other to facilitate inter-chip communications. We compared CMPs using UNION with those using a matched electronic counterpart in 45 nm process. Based on eight applications, simulation results show that on average UNION improves CMP performance by 3.1X while reducing 92% of network energy consumption and 52% of communication delay.","PeriodicalId":306717,"journal":{"name":"2010 IEEE/ACM International Symposium on Nanoscale Architectures","volume":"563 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116283339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast equivalence-checking for quantum circuits","authors":"S. Yamashita, I. Markov","doi":"10.26421/QIC10.9-10-1","DOIUrl":"https://doi.org/10.26421/QIC10.9-10-1","url":null,"abstract":"We perform formal verification of quantum circuits by integrating several techniques specialized to particular classes of circuits. Our verification methodology is based on the new notion of a reversible miter that allows one to leverage existing techniques for simplification of quantum circuits. For reversible circuits which arise as runtime bottlenecks of key quantum algorithms, we develop several verification techniques and empirically compare them. We also extend existing quantum verification tools using SAT-solvers. Experiments with circuits for Shor's number-factoring algorithm, containing thousands of gates, show improvements in efficiency by four orders of magnitude.","PeriodicalId":306717,"journal":{"name":"2010 IEEE/ACM International Symposium on Nanoscale Architectures","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122644770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}