Towards logic functions as the device

Prasad Shabadi, A. Khitun, P. Narayanan, M. Bao, I. Koren, Kang L. Wang, C. A. Moritz
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引用次数: 27

Abstract

This paper argues for alternate state variables and new types of sophisticated devices that implement more functionality in one computational step than typical devices based on simple switches. Elementary excitations in solids enabling wave interactions are possible initial candidates to create such new devices. The paper focuses on magnon-based spin-wave-logic functions (SPWF) and presents high fan-in majority, weighted high fan-in majority, and frequency-multiplexed weighted high fan-in majority devices as initial SPWFs. Experiments proving feasibility are also shown. Benefits vs. scaled CMOS are quantified. Results show that for 128 or larger inputs even a 2.5µm SPWF carry-look-ahead adder implementation is faster than the 45nm CMOS version. The 45nm SPWF adder is expected to be significantly faster across the whole range of input widths. In particular, the 45nm SPWF CLA adder is estimated to be at least 77X faster than CMOS version for input widths equal to or greater than 1024. A second example of a counter circuit is presented to illustrate the considerable reduction in complexity possible vs. CMOS.
向着逻辑功能作为器件
本文讨论了替代状态变量和新型复杂设备,这些设备在一个计算步骤中实现比基于简单开关的典型设备更多的功能。固体中使波相互作用的初等激发可能是创建这种新装置的初始候选者。本文重点研究了基于磁振子的自旋波逻辑函数(SPWF),并提出了高扇入多数、加权高扇入多数和频率复用加权高扇入多数器件作为初始SPWF。实验证明了该方法的可行性。与缩放CMOS相比,优势是量化的。结果表明,对于128或更大的输入,即使是2.5µm SPWF进位前置加法器的实现也比45nm CMOS版本更快。在整个输入宽度范围内,45nm SPWF加法器的速度有望显著提高。特别是,当输入宽度等于或大于1024时,估计45nm SPWF CLA加法器比CMOS版本至少快77X。第二个反电路的例子被提出,以说明相当大的复杂性降低可能与CMOS。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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