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4th IEEE International Workshop on System-on-Chip for Real-Time Applications最新文献

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A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter 具有像素级模数转换器和可重构SRAM/计数器的数字CMOS成像仪
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319845
Yat-Fong Yung, A. Bermak
{"title":"A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter","authors":"Yat-Fong Yung, A. Bermak","doi":"10.1109/IWSOC.2004.1319845","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319845","url":null,"abstract":"In this paper a CMOS image sensor with on-pixel analog-to-digital converter based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel form 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated with the switching activities of the global data bus lines are reduced. Besides 8-bit precision, the imager can also be configured to 4-bit precision for low resolution frame rate and decreasing overall power consumption. A prototype chip was realized in Alcatel 0.35/spl mu/m CMOS technology. Each pixel occupies an area of 46/spl mu/m x 48/spl mu/m with a fill-factor of 14%.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121078463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Observability-based RTL simulation using Java 使用Java的基于可观察性的RTL模拟
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319874
S. Aly, A. Salem
{"title":"Observability-based RTL simulation using Java","authors":"S. Aly, A. Salem","doi":"10.1109/IWSOC.2004.1319874","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319874","url":null,"abstract":"In this article, a set of Java classes and description styles are proposed to allow the use of the language to specify and simulate RTL descriptions. Components are made reactive to signals using Java observability. A clock is modeled using the multithreaded features of Java. The proposed classes and styles, named RTLJava, implement a cycle-based simulator by defining a notifying-set method for the signal class and both set and update methods for the registers. The steady state of a signal may take several simulation cycles until no further new notifications of signal value changes are reported. The proposed methodology allows both behavioral and structural descriptions of RTL circuits.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"653 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117104410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A programmable base MDLNS MAC with self-generated lookup table 具有自生成查找表的可编程基础MDLNS MAC
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319850
Wenjing Zhang, G. Jullien, V. Dimitrov
{"title":"A programmable base MDLNS MAC with self-generated lookup table","authors":"Wenjing Zhang, G. Jullien, V. Dimitrov","doi":"10.1109/IWSOC.2004.1319850","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319850","url":null,"abstract":"This paper presents an new architecture for a programmable second base multi-dimensional logarithmic number system (MDLNS) multiply accumulator cell (MAC) using DRAM to store the conversion lookup table (LUT). It uses a direct mapping from nonbinary exponents to binary format with a more than 50% reduction in DRAM size compared to a recently reported architecture. With a simple modification of the DRAM data loading structure, each MAC can build its own LUT specific to the nonbinary exponents of the corresponding MDLNS coefficient in a pipelined data flow. This results not only in a considerable reduction of DRAM size, but also in the elimination of adders normally required for computing non-binary exponents in a data filtering channel.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116098711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel memory architecture for real-time mesh-based video motion compensation 一种新的基于网格的实时视频运动补偿存储结构
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.11
M. Sayed, Wael Badawy
{"title":"A novel memory architecture for real-time mesh-based video motion compensation","authors":"M. Sayed, Wael Badawy","doi":"10.1109/IWSOC.2004.11","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.11","url":null,"abstract":"This paper presents a memory architecture for real-time mesh-based video motion compensation. The architecture uses the affine transformation for warping the deformed patches in the reference frame into the undeformed patches in the current frame. The reference and current frames are stored in SRAMs generated with Virage/spl trade/ memory compiler. The proposed architecture has been prototyped, simulated and synthesized using the TSMC 0.18 /spl mu/m CMOS technology. At 100 MHz clock frequency, the proposed architecture processes one CIF video frame (i.e. 352x288 pixels) in 0.59 ms. This means it can process up to 1694 frames per second. The core area of the proposed architecture is 28.04 mm/sup 2/ and its power consumption is 31.15 mW.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116102508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SOC design of an IF subsampling terminal for a gigabit wireless LAN with asymmetric equalization 非对称均衡千兆无线局域网中频子采样终端的SOC设计
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319899
H. Pekau, J. Nakaska, J. Kulyk, G. McGibney, J. Haslett
{"title":"SOC design of an IF subsampling terminal for a gigabit wireless LAN with asymmetric equalization","authors":"H. Pekau, J. Nakaska, J. Kulyk, G. McGibney, J. Haslett","doi":"10.1109/IWSOC.2004.1319899","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319899","url":null,"abstract":"The design of a simple IF subsampling terminal for a gigabit wireless local area network is presented. All equalization is performed in the base station, allowing the terminal to be implemented using simplified hardware without any digital signal processing. System design of the WLAN terminal is discussed and simulation results are presented for an SOC implementation of the terminal receiver with realistic block specifications. The WLAN uses 16-QAM modulation with a data rate of 1.6Gbit/s, and has a 400MHz signal bandwidth modulated on a 10.4GHz carrier, down-converted to an intermediate frequency of 800MHz.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115381492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A parameterized cell-based design approach for digital-to-analog converters 基于参数化单元的数模转换器设计方法
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319883
K. Andersson, M. Vesterbacka
{"title":"A parameterized cell-based design approach for digital-to-analog converters","authors":"K. Andersson, M. Vesterbacka","doi":"10.1109/IWSOC.2004.1319883","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319883","url":null,"abstract":"Due to the lack of proper design automation tools, designers are often forced to use full-custom design methodologies when designing analog and mixed-signal circuits. In this work, we discuss a design methodology based on parameterized cells intended for efficient design. The methodology is illustrated with the design of a 12-bit configurable current-steering DAC. Because the cells are parameterized, their layout must be described in a generalized way, resulting in a longer design time compared with a manual layout of a fixed circuit. However, the parameterized approach simplifies iteration of the layout process and block reuse.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126799960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Accurate on-chip variation modeling to achieve design for manufacturability 精确的片上变化建模，实现可制造性设计
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319882
Keh-Jeng Chang
{"title":"Accurate on-chip variation modeling to achieve design for manufacturability","authors":"Keh-Jeng Chang","doi":"10.1109/IWSOC.2004.1319882","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319882","url":null,"abstract":"Undesired on-chip variations (OCV) become more prominent in scaled technologies. They decrease VLSI/SoC yields even though three design-for-manufacturability (DFM) techniques have been widely adopted by CMOS foundries to enhance the uniformity of copper-based interconnect. A new modeling and DFM analysis methodology is therefore proposed to accurately characterize the OCV from the perspective of circuit parameters rather than from that of process parameters. The resulting OCV is more straightforward and easier to be implemented in the mainstream electronic design automation (EDA) design flows to insure high yields.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124446623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Possible noise failure modes in static and dynamic circuits 静态和动态电路中可能的噪声失效模式
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319863
M. Chowdhury, Y. Ismail
{"title":"Possible noise failure modes in static and dynamic circuits","authors":"M. Chowdhury, Y. Ismail","doi":"10.1109/IWSOC.2004.1319863","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319863","url":null,"abstract":"This paper investigates possible failure modes in both dynamic and static CMOS digital circuits due to noise disturbance. In current VLSI circuits, where mixture of static and dynamic implementation is very common, it is important to identify possible noise failure modes to help designers develop techniques to prevent such failures. Injection of noise causes temporary or permanent signal deviation on a circuit node depending on the level of noise and the affected circuit. The deviation of signal level of the circuit node may lead to functional failure in digital circuits, particularly in dynamic circuit families. Static circuits are inherently robust and can effectively restore the signal deviation before having undesired logic shift. However, some static circuits with a feedback loop cannot recover from noise-induced errors.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128190868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ultra low noise signed digit arithmetic using cellular neural networks 基于细胞神经网络的超低噪声符号数字算法
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319866
Y. Ibrahim, G. Jullien, W. Miller
{"title":"Ultra low noise signed digit arithmetic using cellular neural networks","authors":"Y. Ibrahim, G. Jullien, W. Miller","doi":"10.1109/IWSOC.2004.1319866","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319866","url":null,"abstract":"This paper addresses mixed-signal applications where the presence of digital switching noise is a major problem; for example, digital circuitry adjacent to sensitive bio-sensors in an SoC device. This paper describes a method for building ultra low-noise signed-digit arithmetic circuits using analog cellular neural networks, essentially implementing asynchronous digital logic with analog circuits. Each node in our asynchronous architectures uses controlled current sources driving into capacitors; providing both low current and voltage time derivatives (di/dt and dv/dt) and, as a result, reducing both instantaneous and average system and cross-talk noise. In this paper, we present the architecture of a signed-digit radix-2 adder with symmetrical digit set {-1,0,1}. The adder uses a new class of CNNs that has three stable states to match the three values of the digit set. The adder not only has all the known advantages of SD addition, but also greatly reduces switching noise. We also describe a 32x32-digit multiplier based on this technique. In a simulated comparison with CMOS digital counterparts in a 0.35/spl mu/m CMOS technology, the peak system noise is 60-70dB lower for the CNN circuits.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"9 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114001111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Simulation-in-the-loop analog circuit sizing method using adaptive model-based simulated annealing 基于自适应模型的模拟退火在环模拟电路定径方法
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319864
Donghoon Han, A. Chatterjee
{"title":"Simulation-in-the-loop analog circuit sizing method using adaptive model-based simulated annealing","authors":"Donghoon Han, A. Chatterjee","doi":"10.1109/IWSOC.2004.1319864","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319864","url":null,"abstract":"In this paper, we propose a novel simulation-based analog circuit sizing method, which is capable of significantly reducing the computational cost via adaptive response surface modeling. The proposed algorithm is based on the selective evaluation of a response surface model coupled with numerical circuit simulation and the adaptive update of the model for accuracy. Efficient sampling scheme for modeling, that is crucial for speedup and convergence into the optimum solution, is done with two criteria cascaded. One provides sufficient samples for model accuracy and convergence, whereas the other is designed to avoid over-sampling. Multivariate adaptive regression splines (MARS) is used to construct a model of an arbitrary cost function. For the demonstration of efficiency and validity of the proposed method, we apply it to several test functions and a practical circuit sizing case.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133771052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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