Simulation-in-the-loop analog circuit sizing method using adaptive model-based simulated annealing

Abstract

In this paper, we propose a novel simulation-based analog circuit sizing method, which is capable of significantly reducing the computational cost via adaptive response surface modeling. The proposed algorithm is based on the selective evaluation of a response surface model coupled with numerical circuit simulation and the adaptive update of the model for accuracy. Efficient sampling scheme for modeling, that is crucial for speedup and convergence into the optimum solution, is done with two criteria cascaded. One provides sufficient samples for model accuracy and convergence, whereas the other is designed to avoid over-sampling. Multivariate adaptive regression splines (MARS) is used to construct a model of an arbitrary cost function. For the demonstration of efficiency and validity of the proposed method, we apply it to several test functions and a practical circuit sizing case.