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4th IEEE International Workshop on System-on-Chip for Real-Time Applications最新文献

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Using design patterns for type unification and introspection in SystemC 在SystemC中使用类型统一和自省的设计模式
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319847
L. Charest, E. Aboulhamid, G. Bois
{"title":"Using design patterns for type unification and introspection in SystemC","authors":"L. Charest, E. Aboulhamid, G. Bois","doi":"10.1109/IWSOC.2004.1319847","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319847","url":null,"abstract":"Reflective environments such as .NET have provided programmers with the ability to gain access to a program structural information with ease. Reflectivity allows program metadata to be accessible at runtime. C++ is perceived by many to be a well-balanced language; it combines elegant software constructs and raw execution speed. Due to C++ success, many hardware engineers are moving away for traditional solution such as VHDL to new ones such as System. Since SystemC is based on C++, it is lacking some of the advanced features and concepts available in modern languages. For this raison, our team has built a system-level modeling environment called Esys.Net that is based on .Net and C#. We are now looking at interoperability avenues between ESys.Net and SystemC. We propose a solution that, through data introspection, could greatly ease interoperability between SystemC and other environments (and tools) such as ESys.Net, while avoiding the RTTI (Run Time Type Information) library.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129069854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
64-bit hybrid dual-threshold voltage power-aware conditional carry adder design 64位混合双阈值电压功率感知条件进位加法器设计
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319851
Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang
{"title":"64-bit hybrid dual-threshold voltage power-aware conditional carry adder design","authors":"Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang","doi":"10.1109/IWSOC.2004.1319851","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319851","url":null,"abstract":"A 64-bit hybrid dual-threshold conditional-carry adder for power-aware applications was presented. Components on critical paths use a low threshold voltage to accelerate the speed of operation. Other components use the normal threshold voltage to save power. This is attractive in implementing power-aware arithmetic systems. The proposed circuit has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance. Its power efficiency is better than that of the single threshold voltage circuit designs.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125735955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A sigma-delta modulator for digital hearing instruments using 0.18/spl mu/m CMOS technology 采用0.18/spl mu/m CMOS技术的数字助听器sigma-delta调制器
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.17
I. Taha, M. Ahmadi, W. Miller
{"title":"A sigma-delta modulator for digital hearing instruments using 0.18/spl mu/m CMOS technology","authors":"I. Taha, M. Ahmadi, W. Miller","doi":"10.1109/IWSOC.2004.17","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.17","url":null,"abstract":"This paper examines the design and implementation of a single-loop second-order CMOS sigma-delta modulator for digital audio hearing-aid applications. The modulator circuit features reduced complexity, area reduction and low conversion energy. It has a sampling rate of 8.2MHz with an over-sampling ratio (OSR) of 256 to provide an audio bandwidth of 16kHz. The modulator is implemented in a 0.18/spl mu/m CMOS technology with metal-to-metal sandwich structure capacitors. It operates with a supply voltage of 1.8V. The active area is 0.403 mm/sup 2/. The modulator achieves a 98dB signal-to-noise-and-distortion ratio (SNDR) and a 100dB dynamic range (DR) at a Nyquist conversion rate of 32kHz and consumes 1321 /spl mu/W with a joule/conversion figure of merit equal to 161x10/sup -12/J/s.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114470854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An accurate low iteration algorithm for effective capacitance computation 有效电容计算的精确低迭代算法
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1142/S0218126607003897
Shizhong Mei, Y. Ismail
{"title":"An accurate low iteration algorithm for effective capacitance computation","authors":"Shizhong Mei, Y. Ismail","doi":"10.1142/S0218126607003897","DOIUrl":"https://doi.org/10.1142/S0218126607003897","url":null,"abstract":"This paper presents an efficient and accurate approach to calculate effective capacitances in the presence of RC interconnect loads. In the pre-characterization process, the gate model is selected such that the output of the model matches both the delay and the shape of the real gate response. In order to determine the effective capacitance, a novel algorithm is developed to efficiently and accurately calculate the propagation delay from circuit elements. This algorithm requires at most two iterations to obtain effective capacitances that produce gate delays within 4% of HSPICE results. This is at most half the time required by the currently used method to calculate effective capacitances.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114751660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Taking mixed-signal substrate noise coupling simulation to the behavioral level using SystemC 利用SystemC将混合信号基板噪声耦合仿真提升到行为层面
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.65
J. Lundgren, T. Ytterdal, K. Vonbun, M. O’nils
{"title":"Taking mixed-signal substrate noise coupling simulation to the behavioral level using SystemC","authors":"J. Lundgren, T. Ytterdal, K. Vonbun, M. O’nils","doi":"10.1109/IWSOC.2004.65","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.65","url":null,"abstract":"We present methods and models to simulate substrate noise coupling at the behavioral level. The models are implemented as a part of the SystemC based behavioral level noise coupling (BeNoC) simulation application. The application is designed as a wrapper to SystemC component modules, enabling designers to simulate substrate noise coupling in their modules during the entire circuit refinement process. This is enabled through the two main contributions presented in this paper: (1) methods to connect the behavioral level with low level circuit simulations and (2) generation of a fast and accurate circuit model for substrate coupling simulations. The accuracy of the generated substrate noise coupling model is verified against device simulations. The same verification test case is used to demonstrate the connection between behavioral simulations and circuit simulations.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125602071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An intellectual property module for auto-calibration of time-interleaved pipelined analog-to-digital converters 一个知识产权模块，用于时间交错流水线模数转换器的自动校准
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319860
D. Morin, F. Normandin, M. Grandmaison, H. Dang, Y. Savaria, M. Sawan
{"title":"An intellectual property module for auto-calibration of time-interleaved pipelined analog-to-digital converters","authors":"D. Morin, F. Normandin, M. Grandmaison, H. Dang, Y. Savaria, M. Sawan","doi":"10.1109/IWSOC.2004.1319860","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319860","url":null,"abstract":"A flexible digital intellectual property (IP) module that controls the auto-calibration of time interleaved pipelined ADCs is presented. It takes advantage of a judicious combination of classical calibration techniques to determine, in an adaptive way, the adequate compensation of gain and offset for each stage of interleaved pipelined ADCs. A novel built-in self-test (BIST) is also included in the IP. Preliminary simulation results confirm the expected behavior of the calibration method. This soft IP was designed and synthesized.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117298379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A real-time architecture of SOC selective gas sensor array using KNN based on the dynamic slope and the steady state response 基于动态斜率和稳态响应的KNN的SOC选择性气体传感器阵列实时结构
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319844
M. Shi, A. Bermak, S. Brahim-Belhouari
{"title":"A real-time architecture of SOC selective gas sensor array using KNN based on the dynamic slope and the steady state response","authors":"M. Shi, A. Bermak, S. Brahim-Belhouari","doi":"10.1109/IWSOC.2004.1319844","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319844","url":null,"abstract":"This paper demonstrates that using the dynamic response together with the steady state response greatly improves the classification performance of gas sensors. We propose a SOC VLSI architecture based on the KNN algorithm and operating on both the steady state and dynamic slope response of the data from the gas sensor array. The architecture is based on a current model analog pipelining strategy which allows to share hardware resources between different sensors within the sensor array. This results in significant area savings making the prospect of building low cost and real-time electronic nose microsystem reasonably cheap.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125813408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
CRT-based three-prime RSA with immunity against hardware fault attack 基于crt的抗硬件故障攻击的三素数RSA
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.31
Yonghong Yang, Z. Abid, Wei Wang
{"title":"CRT-based three-prime RSA with immunity against hardware fault attack","authors":"Yonghong Yang, Z. Abid, Wei Wang","doi":"10.1109/IWSOC.2004.31","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.31","url":null,"abstract":"In this paper, we carry out the study of the Chinese remainder theorem based three-prime RSA cryptosystem. The hardware fault attack on three-prime RSA cryptosystem is analyzed and it is proven that the three-prime RSA is more difficult to be broken than two-prime RSA by the hardware fault attack. Then, Shamir's checking procedure is extended from two-prime to three-prime RSA to increase its immunity against such attack. Finally an immune method for three-prime RSA without checking procedure is proposed in this paper, which is more efficient than the previous methods. It is expected that this proposed system will play an important role in the future cryptography applications.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122871641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Towards automating hardware/software co-design 迈向自动化硬件/软件协同设计
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319876
M. El-Kharashi, M. H. El-Malaki, S. Hammad, A. Salem, A. Wahdan
{"title":"Towards automating hardware/software co-design","authors":"M. El-Kharashi, M. H. El-Malaki, S. Hammad, A. Salem, A. Wahdan","doi":"10.1109/IWSOC.2004.1319876","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319876","url":null,"abstract":"We propose a new flow for hardware/software co-design that forms a base for further automation attempts of the co-design process. Our proposed flow starts with a software-only solution in which all system functionality is described as embedded software written in C targeting a selected platform. Then, the flow iterates through co-verification, profiling, partitioning, and co-synthesis until the design criteria are met. We present two test cases to show the effectiveness of our proposed methodology.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115842917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Verification strategy determination using dependence analysis of transaction-level models 使用事务级模型的依赖性分析确定验证策略
4th IEEE International Workshop on System-on-Chip for Real-Time Applications Pub Date : 2004-07-19 DOI: 10.1109/IWSOC.2004.1319856
S. Regimbal, Y. Savaria, G. Bois
{"title":"Verification strategy determination using dependence analysis of transaction-level models","authors":"S. Regimbal, Y. Savaria, G. Bois","doi":"10.1109/IWSOC.2004.1319856","DOIUrl":"https://doi.org/10.1109/IWSOC.2004.1319856","url":null,"abstract":"It is well known that functional verification is a real bottleneck in any digital design development. A robust verification strategy should specify which testbenches are required to verify a system. With a modular system, the determination of which testbenches are required to confirm successful integration of each module is generally done in an ad-hoc fashion. In this paper, we propose a systematic approach supported by a tool to determine effective module combinations that should be verified when integrating a modular system. A goal of verification being to detect errors, it is valuable to create the most favorable situation to detect them. Our proposed approach is based on a static dependence analysis of a transaction-level model and the evaluation of module combinations using a verifiability metric. Using our methodology, we are able to provide quantitative results in order to help verification engineers determine which module combinations are the most appropriate for integration.","PeriodicalId":306688,"journal":{"name":"4th IEEE International Workshop on System-on-Chip for Real-Time Applications","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124782850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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