64-bit hybrid dual-threshold voltage power-aware conditional carry adder design

Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang
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Abstract

A 64-bit hybrid dual-threshold conditional-carry adder for power-aware applications was presented. Components on critical paths use a low threshold voltage to accelerate the speed of operation. Other components use the normal threshold voltage to save power. This is attractive in implementing power-aware arithmetic systems. The proposed circuit has the lowest power-delay product and energy-delay product. The hybrid circuit represents a fine compromise between power and performance. Its power efficiency is better than that of the single threshold voltage circuit designs.
64位混合双阈值电压功率感知条件进位加法器设计
提出了一种适用于功耗感知应用的64位混合式双门限条件进位加法器。关键路径上的组件使用低阈值电压来加快运行速度。其他组件采用正常阈值电压,以节省功耗。这在实现功率感知的算术系统中很有吸引力。该电路具有最低的功率延迟积和能量延迟积。混合电路在功率和性能之间取得了很好的折衷。其功率效率优于单阈值电压电路设计。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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