Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference最新文献

A single-pass, in-situ planarization process utilizing TEOS for double-poly, double-metal CMOS technologies 一种利用TEOS进行双聚双金属CMOS技术的单道原位平面化工艺

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78009

S. Mehta, G. Sharma

引用次数: 0

Transmission characteristics of narrow line-width interconnections on silicon substrates 硅衬底上窄线宽互连的传输特性

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78004

C. J. Scott

引用次数: 1

Low-resistance submicron CVD W interlevel via plugs on Al-Cu-Si 低电阻亚微米CVD W间通过插头铝铜硅

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78013

R. Joshi, S. Brodsky, T. Bucelot, M. Jaso, R. Uttecht

{"title":"Low-resistance submicron CVD W interlevel via plugs on Al-Cu-Si","authors":"R. Joshi, S. Brodsky, T. Bucelot, M. Jaso, R. Uttecht","doi":"10.1109/VMIC.1989.78013","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78013","url":null,"abstract":"The most critical issues of interfacial contact between CVD (chemical vapor deposition) W and Al-Cu-Si in submicron vias using SiH/sub 4/ and H/sub 2/ reduction of WF/sub 6/ are addressed. The effect of process parameters of selective CVD W, especially when deposited by SiH/sub 4/-based chemistry, on contact resistance to Al-Cu-Si is evaluated for the first time. It is observed that out of all process parameters the deposition temperature affects the contact resistance the most. As the deposition temperature increases, the contact resistance of the stack W/Al-Cu-Si decreases. Specific resistivities, as low as 3-5*10/sup -9/ Omega cm/sup 2/, are realized at turret temperatures of 550 degrees C. On the other hand, the contact resistances are relatively unaffected by partial pressures of SiH/sub 4/ or WF/sub 6/. As a result the growth rates which are dependent on partial pressures do not control the contact resistances. Phosphoric-chromic and buffered hydrofluoric acid cleanings combined with higher deposition temperatures yield relatively superior contact resistance compared to other cleaning techniques.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124902497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An improved interlevel dielectric process for submicron double-level metal products 一种改进的亚微米双级金属制品的层间介电工艺

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.77994

S. Pennington, S. Luce, D.P. Hallock

引用次数: 3

Improved excimer laser planarization of AlSi with addition of Ti or Cu 添加Ti或Cu改善AlSi准分子激光平面化

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.77989

B. Woratschek, P. Carey, M. Stolz, F. Bachmann

引用次数: 3

A comparison of a two layer metal system built with selective CVD W plugs and elevated temperature, sputtered Al(Cu) 选择性CVD W塞和高温溅射Al(Cu)两层金属体系的比较

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78047

S. R. Wilson, R. J. Mattox, J. Sellers

{"title":"A comparison of a two layer metal system built with selective CVD W plugs and elevated temperature, sputtered Al(Cu)","authors":"S. R. Wilson, R. J. Mattox, J. Sellers","doi":"10.1109/VMIC.1989.78047","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78047","url":null,"abstract":"Summary form only given. Advanced ULSI circuits require minimum features <or=1.0 mu m to maximize packing density. In addition, metal line pinches must be approximately 2.0 mu m and vias <or=1.0 mu m with straight walls. Thicker interlevel dielectrics for capacitance reduction mean that the aspect ratio (height/width) of vias must be approximately 1.0. These high aspect ratios greatly reduce the step coverage of sputtered metal causing two potential problems: (1) increased via resistance and (2) sources of reliability failure. To study these issues, the authors used a double-level metal vehicle with a range of metal 1 pitch of 1.75-3.0 mu m, a metal 2 pitch range of 3.0-4.5 mu m, and a range of via sizes from (0.75 mu m)/sup 2/ to (1.5 mu m)/sup 2/. The via chains using W to achieve an approximately 100% via fill had excellent results. All chains were continuous and the average resistance/via was 0.33, 0.19 and 0.13 Omega for the (0.75 mu m)/sup 2/, (1.0 mu m)/sup 2/, and (1.25 mu m)/sup 2/ via chains, respectively. The standard deviation across a wafer in each case was less than 2%. When the Wfills were 75% on the smallest vias the step coverage from 325 degrees C sputtered AlCu was poor; causing some opens and an increase in the mean and standard deviation of the Omega /via. On larger vias with same percent fill, the chains were continuous, but the resistance was greater than for the 100% fills. This is an issue when the vias have different depths due to underlying topography.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122622964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Evaluation of a novel passivation process for submicron CMOS SRAMs using PETEOS in combination with other PECVD films 利用PETEOS与其他PECVD膜相结合的新型亚微米CMOS sram钝化工艺的评价

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.77995

W. Gootzen, M. Bellersen, L. D. Bruin, G. Rao, G. Rutten, D.L.W. Yen

引用次数: 1

Impact of Al melting on diode integrity 铝熔化对二极管完整性的影响

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78022

A. Kamgar, R. Knoell, F. Baiocchi, K. Orlowsky, K. Cheung, R. Liu

引用次数: 0

Via electromigration performance of Ti/W/Al-Cu(2%) multilayered metallization 研究了Ti/W/Al-Cu(2%)多层金属化的电迁移性能

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78063

C. Martin, J. McPherson

引用次数: 10

Step coverage prediction in plasma-enhanced deposition of silicon dioxide from TEOS 等离子体增强TEOS中二氧化硅沉积的步长覆盖预测

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78042

G. Raupp, T. Cale, H. Hey

引用次数: 1