{"title":"An improved interlevel dielectric process for submicron double-level metal products","authors":"S. Pennington, S. Luce, D.P. Hallock","doi":"10.1109/VMIC.1989.77994","DOIUrl":null,"url":null,"abstract":"An improved interlevel dielectric (ILD) deposition process is presented for submicron double-level metal products that use a multichamber tool capable of doing both CVD film deposition and etching. This multistep, multitool process has now been integrated into a single cassette-to-cassette operation. By using both plasma-enhanced and thermal CVD TEOS oxide films together with argon sputtering and anisotropic oxide etching, an effective low-temperature, void-free interlevel dielectric is formed in a manner that also reduces wafer handling and process queuing time.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VMIC.1989.77994","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
An improved interlevel dielectric (ILD) deposition process is presented for submicron double-level metal products that use a multichamber tool capable of doing both CVD film deposition and etching. This multistep, multitool process has now been integrated into a single cassette-to-cassette operation. By using both plasma-enhanced and thermal CVD TEOS oxide films together with argon sputtering and anisotropic oxide etching, an effective low-temperature, void-free interlevel dielectric is formed in a manner that also reduces wafer handling and process queuing time.<>