A single-pass, in-situ planarization process utilizing TEOS for double-poly, double-metal CMOS technologies

Abstract

A planarization technique utilizing in situ etching of TEOS-based CVD oxide is presented. The process includes TEOS/O/sub 2/-based PECVD oxide, TEOS/O/sub 3/-based LPCVD oxide, Ar/sup +/ sputter etching, and CF/sub 4/-based reactive ion etching, all in a single pumpdown. This planarization process has been successfully used to fabricate advanced double-poly double-metal circuits on 0.8- mu m CMOS technologies. E-test structures indicate low via resistance (0.15 Omega /via) and the absence of any metal opens or shorts. Custom-designed defect monitors show extremely low defect densities for both vias and metal. Comparison of die yields for the new in situ TEOS-etchback process and an SOG-etchback process indicates that much higher yields can be obtained by the use of the new process.<>