Evaluation of a novel passivation process for submicron CMOS SRAMs using PETEOS in combination with other PECVD films

Abstract

The final passivation layer affects the electrical behavior of a device and also influences various failure mechanisms in device, package, and product reliability by its interaction with the metal layers underneath and the packaging material above it. In order to address the various issues involved, several passivation schemes have been evaluated. A scheme using PECVD-TEOS in combination with other PECVD films for the 0.7- mu m and 0.5- mu m CMOS SRAM processes is proposed.<>