一种改进的亚微米双级金属制品的层间介电工艺

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI:10.1109/VMIC.1989.77994

S. Pennington, S. Luce, D.P. Hallock

{"title":"一种改进的亚微米双级金属制品的层间介电工艺","authors":"S. Pennington, S. Luce, D.P. Hallock","doi":"10.1109/VMIC.1989.77994","DOIUrl":null,"url":null,"abstract":"An improved interlevel dielectric (ILD) deposition process is presented for submicron double-level metal products that use a multichamber tool capable of doing both CVD film deposition and etching. This multistep, multitool process has now been integrated into a single cassette-to-cassette operation. By using both plasma-enhanced and thermal CVD TEOS oxide films together with argon sputtering and anisotropic oxide etching, an effective low-temperature, void-free interlevel dielectric is formed in a manner that also reduces wafer handling and process queuing time.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"An improved interlevel dielectric process for submicron double-level metal products\",\"authors\":\"S. Pennington, S. Luce, D.P. Hallock\",\"doi\":\"10.1109/VMIC.1989.77994\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An improved interlevel dielectric (ILD) deposition process is presented for submicron double-level metal products that use a multichamber tool capable of doing both CVD film deposition and etching. This multistep, multitool process has now been integrated into a single cassette-to-cassette operation. By using both plasma-enhanced and thermal CVD TEOS oxide films together with argon sputtering and anisotropic oxide etching, an effective low-temperature, void-free interlevel dielectric is formed in a manner that also reduces wafer handling and process queuing time.<<ETX>>\",\"PeriodicalId\":302853,\"journal\":{\"name\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VMIC.1989.77994\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VMIC.1989.77994","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

提出了一种改进的层间介电沉积(ILD)工艺，用于亚微米双级金属产品，该工艺使用多室工具，既能进行CVD膜沉积，又能进行蚀刻。这种多步骤、多工具的过程现在已集成到单个磁带到磁带的操作中。通过使用等离子体增强和热CVD TEOS氧化膜以及氩气溅射和各向异性氧化物蚀刻，形成了有效的低温，无空隙的层间介电体，同时也减少了晶圆处理和工艺排队时间

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An improved interlevel dielectric process for submicron double-level metal products

An improved interlevel dielectric (ILD) deposition process is presented for submicron double-level metal products that use a multichamber tool capable of doing both CVD film deposition and etching. This multistep, multitool process has now been integrated into a single cassette-to-cassette operation. By using both plasma-enhanced and thermal CVD TEOS oxide films together with argon sputtering and anisotropic oxide etching, an effective low-temperature, void-free interlevel dielectric is formed in a manner that also reduces wafer handling and process queuing time.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference

自引率

0.00%

发文量