Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference最新文献_第8页

Electrical properties of polyimides for interlevel isolation and active device gate isolation 层间隔离和有源器件栅极隔离用聚酰亚胺的电性能

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.77999

A. Dubey, D. Lile

引用次数: 3

Low contact resistance polysilicon plug for halfmicron CMOS technology 低接触电阻多晶硅插头半微米CMOS技术

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78017

T. Hamajima, Y. Sugano

引用次数: 2

Field inversion in CMOS double metal circuits due to carbon based SOGs 碳基SOGs在CMOS双金属电路中的场反转

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78037

D. Pramanik, S. Nariani, G. Spadini

引用次数: 12

Low temperature plasma amorphous carbon encapsulation for reliable multilevel interconnections-with applications to wafer scale multichip packaging 低温等离子体非晶碳封装，用于可靠的多级互连-应用于晶圆级多芯片封装

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.77996

J. McDonald, S. Dabral, S. Wu, A. Martı́n, T. Lu

引用次数: 1

Resistive contrast imaging applied to multilevel interconnection failure analysis 电阻对比成像在多级互连故障分析中的应用

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78020

E. I. Cole

引用次数: 19

A study of pulsed laser planarization of aluminum for VLSI metallization 超大规模集成电路金属化用脉冲激光镀铝的研究

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.77992

R. Liu, K. Cheung, W. Lai, R. Heim

{"title":"A study of pulsed laser planarization of aluminum for VLSI metallization","authors":"R. Liu, K. Cheung, W. Lai, R. Heim","doi":"10.1109/VMIC.1989.77992","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77992","url":null,"abstract":"Pulsed laser melting of Al to improve the contact via coverage in VLSI metallization has been investigated for various laser fluences and substrate temperatures. The authors have characterized how the Al flow phenomenon progresses: from melting (recrystallization and grain growth) to planarization (via covered but not necessarily filled), then to via-fill (solidly plugged), and finally from localized to systematic ablation (material loss). The laser energy densities for these conditions have been quantified and the useful range for VLSI application extracted. Without antireflective coating, the process window is +or-6-8% for 0.5- mu m Al film to fill a 1- mu m via with a vertical wall. Localized ablation of the Al film at the high energy limit has been found to be the key factor that controls the process window. This limitation can be explained by the estimated temperature rise of the Al film from melting to planarization and via-fill conditions: very high at 400-500 degrees C and 700-800 degrees C above the melting temperature, respectively. The issues of VLSI applications such as pattern density sensitivity and device integrity have been examined.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123446813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Melt and flow behavior of Al into micron size features using incoherent radiation 用非相干辐射研究铝在微米尺度下的熔化和流动行为

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI: 10.1109/VMIC.1989.78054

A. Kamgar, R. C. Beairsto

{"title":"Melt and flow behavior of Al into micron size features using incoherent radiation","authors":"A. Kamgar, R. C. Beairsto","doi":"10.1109/VMIC.1989.78054","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78054","url":null,"abstract":"Summary form only given. High-aspect-ratio via filling by rapid thermal melting of Al has been achieved, but with two major drawbacks. Pure or 0.5%-Cu-doped Al films 0.5- to 1.5- mu m thick were deposited on two types of wafer. Some wafers were patterned with 0.75- to 2- mu m-deep windows formed into deposited SiO while others have no topography. The Al films were deposited on 90-nm TiN or TiW layers. TiN, TiW or SiO/sub 2/ capping was used on some wafers. By melting Al deposited on several substrates the authors found that molten Al did not wet TiN. The Al balled up and pulled away from the surface. It seemed to wet W:Ti, however, along with a metallurgical reaction between Al, W, and Si resulting in the formation of several alloys of W and Al, as well as W:(Si,Al)/sub 2/. Although Al melts at 660 degrees C it did not flow until temperatures above 800 degrees C were achieved. However, even at these temperatures via-filling was not observed in 0.5- mu m-thick Al films. The authors found that Al thickness of 1 mu m or more was required for filling micron-size vias. The high temperature required for the Al flow which causes junction degradation and the agglomeration of Al film are two severe drawbacks for using the RTA technique in Al planarization.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126116069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Enhanced high performance reliable AlSi/TiW metallization for 1.0 mu m CMOS process 增强高性能可靠的AlSi/TiW金属化1.0 μ m CMOS工艺

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1900-01-01 DOI: 10.1109/vmic.1989.78061

H. Chou, W. Su, J.C. Liou, R. Shiue, H. Tuan

{"title":"Enhanced high performance reliable AlSi/TiW metallization for 1.0 mu m CMOS process","authors":"H. Chou, W. Su, J.C. Liou, R. Shiue, H. Tuan","doi":"10.1109/vmic.1989.78061","DOIUrl":"https://doi.org/10.1109/vmic.1989.78061","url":null,"abstract":"Summary form only given. A reported AlSi/TiW metal system is developed with enhanced performance which is anticipated to upgrade the AlSi/TiW metallization. Standard VLSI process is followed for the contact formation process. Before the AlSi deposition, TiW is deposited and annealed using RTA, at a temperature ranging from 625 degrees C to 700 degrees C. AlSi is deposited over TiW followed by the conventional patterning steps. Relatively low temperature alloy is then adapted either by furnace or RTA. The average P+ contact resistance for a 1.2*1.2 mu m/sup 2/ contact is about 25 ohms as compared to 80 ohms for the conventional process. No junction degradation is observed at all for this higher temperature anneal process. A bonus is that the hillocks can be largely eliminated. The sheet resistivity for AlSi/TiW alloyed at 450 degrees C, 30 min. is twice as large as that for samples alloyed at 410 degrees C, 30 min. or 425 degrees C, 40 sec with RTA. This difference might signal the interaction between AlSi and TiW at 450 degrees C. It is also found that the metal shortening rate bears a relationship to the thickness of TiW.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114587005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Shadow step structures for the analysis of thin film conductors 用于薄膜导体分析的影阶结构

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1900-01-01 DOI: 10.1109/VMIC.1989.78031

W.C. Rosvold

引用次数: 0

Your future in the technology evolution of the 90's 你的未来在90年代的技术发展中

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1900-01-01 DOI: 10.1109/VMIC.1989.78070

G. Madland

引用次数: 0