{"title":"Properties of LPCVD titanium nitride for ULSI metallization","authors":"A. Sherman","doi":"10.1109/VMIC.1989.78051","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78051","url":null,"abstract":"Summary form only given. A report is presented on a low-temperature CVD process (TiCl/sub 4/+NH/sub 3/) for deposition of conformal films, as an alternative to sputtering. Studies have been carried out at pressures of 100-300 mtorr and temperatures of 450-700 degrees C on silicon wafers with a NH/sub 3//TiCl/sub 4/ ratio of 20:1. Deposition rates as high as 1000 AA/min have been observed. Film resistivities as low as 80- Omega -cm have been seen for the thinnest films ( approximately 500 AA). The resistivity increases as the films grow thicker, apparently due to a decrease in their density. The films contain small amounts of chlorine (<4%), oxygen (<6%), and hydrogen (<11%), and have Ti/N ratios close to one. They are crystalline with columnar crystals and are adherent. Contact resistance measurements on p/sup +/ contacts annealed at 500 degrees C gave values of 2-3*10/sup -6/ Omega -cm/sup 2/. Multicontact diodes, under the same conditions, showed less than 1- mu A leakage at 10-V reverse bias.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129645785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Wei, G. Raghavan, M. Dass, M. Frost, T. Brat, D. Fraser
{"title":"Comparison of cobalt and titanium silicides for SALICIDE process and shallow junction formation","authors":"C. Wei, G. Raghavan, M. Dass, M. Frost, T. Brat, D. Fraser","doi":"10.1109/VMIC.1989.78027","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78027","url":null,"abstract":"A comparison of TiSi/sub 2/ and CoSi/sub 2/ for the SALICIDE (self-aligned silicide) process is presented. Both TiSi/sub 2/ and CoSi/sub 2/ are formed by RTA in nitrogen. The comparison is based on the formation kinetics, film properties, process compatibilities, and electrical properties. The results are summarized in table form. Co silicide is found to be a better candidate for use in SALICIDE process for submicron devices because it has a less severe lateral gate-S/D encroachment problem, less sensitivity to oxygen, higher resistivity to dry/wet etch, less film stress, better sheet resistance control, less junction leakage, the capability to form low-resistance polycide, and shallow junctions. However, substrate cleaning must ensure no SiO/sub 2/ on Si surfaces that are to be converted to CoSi/sub 2/.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129844820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Field inversion in CMOS double metal circuits due to carbon based SOGs","authors":"D. Pramanik, S. Nariani, G. Spadini","doi":"10.1109/VMIC.1989.78037","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78037","url":null,"abstract":"The authors have shown that under certain conditions carbon-based spin-on-glasses (SOGs) can cause field inversion leading to failure of devices. The authors formulate a model that explains the leakage. On the basis of this model it is possible to use the carbon-based SOGs in double-metal circuits without field inversion by restricting the amount of SOG by doing an etchback and using a passivation that does not liberate H, such as oxynitride or oxide. Some of the recent dielectric deposition systems can deposit nitride films that evolve little to no H on annealing. It is possible to use inorganic SOGs such as phosphorus-doped silicates and not have the problem at all. However, the issue of cracking with these SOGs is always of concern for reliability. The model raises concerns about the presence of organic compounds in the intermetal dielectric either through the use of organic reactants such as TEOS or inadvertently through the incomplete removal of photoresist during some of the masking steps.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128246931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low temperature plasma amorphous carbon encapsulation for reliable multilevel interconnections-with applications to wafer scale multichip packaging","authors":"J. McDonald, S. Dabral, S. Wu, A. Martı́n, T. Lu","doi":"10.1109/VMIC.1989.77996","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77996","url":null,"abstract":"The possibility of using amorphous carbon as an encapsulant for integrated circuits is investigated. As this is a low-temperature plasma-deposited carbon film, low stresses result. This reduces the possibility of bond wire breakages and stress on the underlying film. Its low-temperature deposition, chemical inactivity, highly electrical insulating properties, and imperviousness to the passage of contaminating gases, liquids, and ions make it a suitable encapsulant for circuits. These properties also make it a potential replacement for silicon nitride. The possibility of using amorphous carbon as a wire encapsulant at interconnect level is also explored.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130676408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Resistive contrast imaging applied to multilevel interconnection failure analysis","authors":"E. I. Cole","doi":"10.1109/VMIC.1989.78020","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78020","url":null,"abstract":"Resistive contrast imaging (RCI) is a new failure analysis technique that uses a scanning electron microscope to generate a relative resistance map of an integrated circuit. The RCI map can be used to localize abrupt changes in resistance and verify continuity. Results using RCI on several two-level interconnection devices are described. The images demonstrate how RCI can be used to differentiate between levels and to localize metal shorts and opens. Methods for improving image quality and level differentiation as well as future development work are discussed.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124475670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A study of pulsed laser planarization of aluminum for VLSI metallization","authors":"R. Liu, K. Cheung, W. Lai, R. Heim","doi":"10.1109/VMIC.1989.77992","DOIUrl":"https://doi.org/10.1109/VMIC.1989.77992","url":null,"abstract":"Pulsed laser melting of Al to improve the contact via coverage in VLSI metallization has been investigated for various laser fluences and substrate temperatures. The authors have characterized how the Al flow phenomenon progresses: from melting (recrystallization and grain growth) to planarization (via covered but not necessarily filled), then to via-fill (solidly plugged), and finally from localized to systematic ablation (material loss). The laser energy densities for these conditions have been quantified and the useful range for VLSI application extracted. Without antireflective coating, the process window is +or-6-8% for 0.5- mu m Al film to fill a 1- mu m via with a vertical wall. Localized ablation of the Al film at the high energy limit has been found to be the key factor that controls the process window. This limitation can be explained by the estimated temperature rise of the Al film from melting to planarization and via-fill conditions: very high at 400-500 degrees C and 700-800 degrees C above the melting temperature, respectively. The issues of VLSI applications such as pattern density sensitivity and device integrity have been examined.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123446813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Melt and flow behavior of Al into micron size features using incoherent radiation","authors":"A. Kamgar, R. C. Beairsto","doi":"10.1109/VMIC.1989.78054","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78054","url":null,"abstract":"Summary form only given. High-aspect-ratio via filling by rapid thermal melting of Al has been achieved, but with two major drawbacks. Pure or 0.5%-Cu-doped Al films 0.5- to 1.5- mu m thick were deposited on two types of wafer. Some wafers were patterned with 0.75- to 2- mu m-deep windows formed into deposited SiO while others have no topography. The Al films were deposited on 90-nm TiN or TiW layers. TiN, TiW or SiO/sub 2/ capping was used on some wafers. By melting Al deposited on several substrates the authors found that molten Al did not wet TiN. The Al balled up and pulled away from the surface. It seemed to wet W:Ti, however, along with a metallurgical reaction between Al, W, and Si resulting in the formation of several alloys of W and Al, as well as W:(Si,Al)/sub 2/. Although Al melts at 660 degrees C it did not flow until temperatures above 800 degrees C were achieved. However, even at these temperatures via-filling was not observed in 0.5- mu m-thick Al films. The authors found that Al thickness of 1 mu m or more was required for filling micron-size vias. The high temperature required for the Al flow which causes junction degradation and the agglomeration of Al film are two severe drawbacks for using the RTA technique in Al planarization.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126116069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enhanced high performance reliable AlSi/TiW metallization for 1.0 mu m CMOS process","authors":"H. Chou, W. Su, J.C. Liou, R. Shiue, H. Tuan","doi":"10.1109/vmic.1989.78061","DOIUrl":"https://doi.org/10.1109/vmic.1989.78061","url":null,"abstract":"Summary form only given. A reported AlSi/TiW metal system is developed with enhanced performance which is anticipated to upgrade the AlSi/TiW metallization. Standard VLSI process is followed for the contact formation process. Before the AlSi deposition, TiW is deposited and annealed using RTA, at a temperature ranging from 625 degrees C to 700 degrees C. AlSi is deposited over TiW followed by the conventional patterning steps. Relatively low temperature alloy is then adapted either by furnace or RTA. The average P+ contact resistance for a 1.2*1.2 mu m/sup 2/ contact is about 25 ohms as compared to 80 ohms for the conventional process. No junction degradation is observed at all for this higher temperature anneal process. A bonus is that the hillocks can be largely eliminated. The sheet resistivity for AlSi/TiW alloyed at 450 degrees C, 30 min. is twice as large as that for samples alloyed at 410 degrees C, 30 min. or 425 degrees C, 40 sec with RTA. This difference might signal the interaction between AlSi and TiW at 450 degrees C. It is also found that the metal shortening rate bears a relationship to the thickness of TiW.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114587005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Shadow step structures for the analysis of thin film conductors","authors":"W.C. Rosvold","doi":"10.1109/VMIC.1989.78031","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78031","url":null,"abstract":"A description is given of research on shadow step structures (3S), which are prepatterned, mesa-type geometries that are electrically self-isolating and self-aligning when overlaid with a conducting film. This basic mesa topography has been historically used as a disposable medium for lift-off metallization and other generic patterning forms. A modification of this technique has recently been useful in providing an analytic tool for the maskless evaluation of as-deposited thin-film conductors. On an experimental basis, 3S is being used as an intermediate means to verify the sheet resistivity and tempco of sichrome resistor films. Also, the formation of electromigration patterns is used as a simplified, nonintrusive alternative to the current fabrication method. The 3S technique is being evaluated for other QTAT analyses including the quantifying of physical film stress and Schottky diodes, together with other bulk silicon devices which evaluate metal-silicon interfaces.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133926620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Your future in the technology evolution of the 90's","authors":"G. Madland","doi":"10.1109/VMIC.1989.78070","DOIUrl":"https://doi.org/10.1109/VMIC.1989.78070","url":null,"abstract":"The purpose of this discussion is to provide some insight into matters that will affect the technologist's career in the coming decade. The author examines some of these factors from the viewpoint of the integrated circuit technologist. The role of production is assessed along with utilization of active devices on top of the silicon integrated circuit. The author argues that for the technologist, the new devices will introduce requirements for additional materials knowledge, additional processing knowledge, greater complexity of test equipment, and additional failure modes.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122640097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}