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2006 IEEE Hot Chips 18 Symposium (HCS)最新文献

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Design of a reusable 1GHz, superscalar ARM processor 可重复使用的1GHz超标量ARM处理器的设计
2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI: 10.1109/HOTCHIPS.2006.7477864
Stephen Hill
{"title":"Design of a reusable 1GHz, superscalar ARM processor","authors":"Stephen Hill","doi":"10.1109/HOTCHIPS.2006.7477864","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2006.7477864","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on the design of a reusable 1GHz, superscalar ARM processor. Some of the specific topics discussed include: an overview of the ARM Cortex-A8 Tiger processor; a comparison of reusability verys redeployability; significance to the Cortex-A8 processor; the effects on design flow and microarchitecture; and the interaction of energy efficiency and reusable design.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128980038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Who owns the living room? 客厅是谁的?
2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI: 10.1109/HOTCHIPS.2006.7477859
A. Messer
{"title":"Who owns the living room?","authors":"A. Messer","doi":"10.1109/HOTCHIPS.2006.7477859","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2006.7477859","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on the market for digital entertainment and mobile computing products for the home market. Some of the specific topics discussed include: technologies and services that serve the home market; digital entertainment and home vision/media products; consumer demand for consumer electronics; home networking designs; amd content copyright and protection consideration.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125984923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The AMD Opteron™ CMP NorthBridge architecture: Now and in the future AMD Opteron™CMP北桥架构:现在和未来
2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI: 10.1109/HOTCHIPS.2006.7477747
Patrick Conway, B. Hughes
{"title":"The AMD Opteron™ CMP NorthBridge architecture: Now and in the future","authors":"Patrick Conway, B. Hughes","doi":"10.1109/HOTCHIPS.2006.7477747","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2006.7477747","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on AMD's Opteron, the company's dual-core 64-bit x86 processor. Some of the specific topics discussed include: the features and system specifications of Opteron; memory management facilities; a comparison of previous and current system architectures; the BorthBridge command processing flow architecture; and planned next generation of processor technologies.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130395720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Blackford: A duall processor chipset for servers and workstatiions Blackford:用于服务器和工作站的双处理器芯片组
2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI: 10.1109/HOTCHIPS.2006.7477875
Kai Cheng, Sundaram Chinthamani, Sivakumar Radhakrishnan, F. Briggs, Kathy Debnath
{"title":"Blackford: A duall processor chipset for servers and workstatiions","authors":"Kai Cheng, Sundaram Chinthamani, Sivakumar Radhakrishnan, F. Briggs, Kathy Debnath","doi":"10.1109/HOTCHIPS.2006.7477875","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2006.7477875","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on Intel's Blackford, a dual processor chipset for servers and workstations. Some of the specific topics discussed include: overview of the Bensley platform; the Blackford North Bridge microarchitectural features; and performance testing and output results.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125911963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research accelerator for multiple processors 多处理器研究加速器
2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI: 10.1109/HOTCHIPS.2006.7477751
D. Patterson, Arvind, K. Asanović, Derek Chiou, J. Hoe, C. Kozyrakis, Shih-Lien Lu, M. Oskin, J. Rabaey, J. Wawrzynek
{"title":"Research accelerator for multiple processors","authors":"D. Patterson, Arvind, K. Asanović, Derek Chiou, J. Hoe, C. Kozyrakis, Shih-Lien Lu, M. Oskin, J. Rabaey, J. Wawrzynek","doi":"10.1109/HOTCHIPS.2006.7477751","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2006.7477751","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on RAMP, or research acclerators for multiple processors. Some of the specific topics discussed include: system specifications and architecture; uniprocessor performance capabilities; RAMP hardware and description language features; RAMP applications development; storage capabilities; and future areas of technological development.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122471750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Micro manipulator array for nano-bioelectronics era 纳米生物电子学时代的微操纵器阵列
2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI: 10.1109/HOTCHIPS.2006.7477869
K. Suzuki, Y. Naruse, H. Funaki, K. Itaya, S. Uchikoga
{"title":"Micro manipulator array for nano-bioelectronics era","authors":"K. Suzuki, Y. Naruse, H. Funaki, K. Itaya, S. Uchikoga","doi":"10.1109/HOTCHIPS.2006.7477869","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2006.7477869","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on micro manipulator arrays for nano-bioelectronic applications. Some of the specific topics discussed include: the special features of a micro manipulator array using a novel MEMS-based structures; the demonstration of direct physical control of the interaction between yeast cells and silica particles in liquid for the first time; the adsorption of the particle to the cell was demonstrated using vibrational energy; and Joule heating energy according to external excitation. These results of these tests show a potential impact in medical fields such as physical antibiotics and cell treatments and next generation bio-electronics schemes.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133704042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An implementation of hardware accelerator using dynamically reconfigurable architecture 采用动态可重构架构的硬件加速器实现
2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI: 10.1109/HOTCHIPS.2006.7477752
Takashi Yoshikawa, Yutaka Yamada, S. Asano
{"title":"An implementation of hardware accelerator using dynamically reconfigurable architecture","authors":"Takashi Yoshikawa, Yutaka Yamada, S. Asano","doi":"10.1109/HOTCHIPS.2006.7477752","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2006.7477752","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on the implementation of hardware accelerator using dynamically reconfigurable architecture. Some of the specific topics discussed include: an overview of the reconfigurable architecture; and application example using the H.264 decoding program; performance evaluation of hardware accelerator technologies; and new areas of technological development.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133047411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Inside Intel® Core microarchitecture 内部英特尔®酷睿微架构
2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI: 10.1109/HOTCHIPS.2006.7477876
Jack Doweck
{"title":"Inside Intel® Core microarchitecture","authors":"Jack Doweck","doi":"10.1109/HOTCHIPS.2006.7477876","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2006.7477876","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on Intel's Core product line's microarchitecture, a new foundation for Intel architecture-based mobile, desktop, and server processors that incorporates advanced innovations which optimize performance over a range of market segments. Some of the specific topics discussed include: the special features and system specifications of Intel Core; memory management and prefetching capabilities; system performance and flexibility; multithreading capabilities; and a summary of key features and processing facilities.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123219070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 82
SH-MobileG1: A single-chip application and dual-mode baseband processor SH-MobileG1:单芯片应用和双模基带处理器
2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI: 10.1109/HOTCHIPS.2006.7477871
Masayuki Ito, T. Irita, E. Yamamoto, Kunihiko Nishiyama, Takao Koike, Yoshihiko Tsuchihashi, Hiroyuki Asano, H. Yagi, S. Tamaki, K. Tatezawa, T. Hattori, S. Yoshioka, K. Ohno
{"title":"SH-MobileG1: A single-chip application and dual-mode baseband processor","authors":"Masayuki Ito, T. Irita, E. Yamamoto, Kunihiko Nishiyama, Takao Koike, Yoshihiko Tsuchihashi, Hiroyuki Asano, H. Yagi, S. Tamaki, K. Tatezawa, T. Hattori, S. Yoshioka, K. Ohno","doi":"10.1109/HOTCHIPS.2006.7477871","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2006.7477871","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on Renesas' SH-MobileG1, a single chip application and dual-mode baseband processor. Some of the specific topics discussed include: presrents an overview of the company and its product line; the architecture of SH-MobileG1; 3 CPU configuration; communications architectures; interrupt control facilities; system control capabilities; and power control and leakage current measurements. Also summarizes the feature features and processing capabilities of the SH-MobileG1 line.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124221205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
The tulsa processor: A dual core large shared-cache Intel® Xeon processor 7000 sequence for the MP server market segment 塔尔萨处理器:双核大型共享缓存英特尔®至强处理器7000序列，用于MP服务器市场细分
2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI: 10.1109/HOTCHIPS.2006.7477873
Jeffrey D. Gilbert, Stephen H. Hunt, Daniel Gunadi, Ganapati Srinivas
{"title":"The tulsa processor: A dual core large shared-cache Intel® Xeon processor 7000 sequence for the MP server market segment","authors":"Jeffrey D. Gilbert, Stephen H. Hunt, Daniel Gunadi, Ganapati Srinivas","doi":"10.1109/HOTCHIPS.2006.7477873","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2006.7477873","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on the Tulsa Processor from Intel. Some of the specific topics discussed include: the special features of the Tulsa processor; applications for its use; processing capabilities; targeted markets for its deployment; paths to multi-core designs; options for multiple core processing; the Tulsa engineering experience based on product implementation and use; system architecture; and tested performance output results.","PeriodicalId":302249,"journal":{"name":"2006 IEEE Hot Chips 18 Symposium (HCS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122273456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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