D. Patterson, Arvind, K. Asanović, Derek Chiou, J. Hoe, C. Kozyrakis, Shih-Lien Lu, M. Oskin, J. Rabaey, J. Wawrzynek
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This article consists of a collection of slides from the author's conference presentation on RAMP, or research acclerators for multiple processors. Some of the specific topics discussed include: system specifications and architecture; uniprocessor performance capabilities; RAMP hardware and description language features; RAMP applications development; storage capabilities; and future areas of technological development.