采用动态可重构架构的硬件加速器实现

2006 IEEE Hot Chips 18 Symposium (HCS) Pub Date : 2006-08-01 DOI:10.1109/HOTCHIPS.2006.7477752

Takashi Yoshikawa, Yutaka Yamada, S. Asano

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引用次数: 1

摘要

本文由作者在关于使用动态可重构架构实现硬件加速器的会议演讲中的幻灯片组成。讨论的一些具体主题包括:可重构架构的概述;以及使用H.264解码程序的应用实例;硬件加速器技术的性能评价以及技术发展的新领域。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An implementation of hardware accelerator using dynamically reconfigurable architecture

This article consists of a collection of slides from the author's conference presentation on the implementation of hardware accelerator using dynamically reconfigurable architecture. Some of the specific topics discussed include: an overview of the reconfigurable architecture; and application example using the H.264 decoding program; performance evaluation of hardware accelerator technologies; and new areas of technological development.

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2006 IEEE Hot Chips 18 Symposium (HCS)

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