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2010 IEEE 14th Workshop on Signal Propagation on Interconnects最新文献

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Multiport measurement and deembedding techniques for crosstalk study in via arrays 通孔阵列中串扰研究的多端口测量和去嵌入技术
2010 IEEE 14th Workshop on Signal Propagation on Interconnects Pub Date : 2010-05-09 DOI: 10.1109/SPI.2010.5483580
M. Kotzev, R. Rímolo-Donadío, H. Brüns, C. Schuster
{"title":"Multiport measurement and deembedding techniques for crosstalk study in via arrays","authors":"M. Kotzev, R. Rímolo-Donadío, H. Brüns, C. Schuster","doi":"10.1109/SPI.2010.5483580","DOIUrl":"https://doi.org/10.1109/SPI.2010.5483580","url":null,"abstract":"In this paper the authors present techniques for crosstalk measurements in via arrays using broadband microprobes and a multiport vector network analyzer. The desegmentation method is used for probe deembedding in the bandwidth from 10 MHz up to 50 GHz. In contrast to the common approach which relies on T-matrices the desegmentation procedure ensures flexible fixture extraction using directly the S-parameter or Z-parameter matrices of the multiport network that has to be deembedded. The main advantage of the deembedding by desegmentation technique is that it does not require any S- to T-parameters conversion and if desired allows stepwise extraction of the embedded error networks. A typical application of the desegmentation method is presented by the authors where in the case of microprobe based measurement the error boxes of the microprobes are obtained at first by the use of a two-tier calibration technique and in the next step the desegmentation is applied to remove their detrimental effect on the measurement data.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131450414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Impact by an orthogonal metal grid upon differential- and common-mode characteristics of coupled lines in PCB technology structures 正交金属栅格对PCB技术结构中耦合线的差模和共模特性的影响
2010 IEEE 14th Workshop on Signal Propagation on Interconnects Pub Date : 2010-05-09 DOI: 10.1109/SPI.2010.5483589
T. Le Gouguec, P. Martin
{"title":"Impact by an orthogonal metal grid upon differential- and common-mode characteristics of coupled lines in PCB technology structures","authors":"T. Le Gouguec, P. Martin","doi":"10.1109/SPI.2010.5483589","DOIUrl":"https://doi.org/10.1109/SPI.2010.5483589","url":null,"abstract":"This paper deals with a rigorous study of the impact by perpendicular metal grids on the characteristics of microstrip and coplanar coupled transmission lines. An electromagnetic analysis shows the variations of the propagation parameters in common and differential modes for each type of lines, in the presence of a metal grid. As transmission zeroes are liable to occur at certain frequencies, in particular in the common mode, we investigated the part played by the most influential grid parameters on these disturbances.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131555418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Passivity-preserving parameterized model order reduction for PEEC based full wave analysis 基于PEEC全波分析的无源保持参数化模型降阶
2010 IEEE 14th Workshop on Signal Propagation on Interconnects Pub Date : 2010-05-09 DOI: 10.1109/SPI.2010.5483571
F. Ferranti, G. Antonini, T. Dhaene, L. Knockaert
{"title":"Passivity-preserving parameterized model order reduction for PEEC based full wave analysis","authors":"F. Ferranti, G. Antonini, T. Dhaene, L. Knockaert","doi":"10.1109/SPI.2010.5483571","DOIUrl":"https://doi.org/10.1109/SPI.2010.5483571","url":null,"abstract":"We present a novel parameterized model order reduction technique applicable to the Partial Element Equivalent Circuit method that is able to generate parametric reduced order models, stable and passive by construction, over a user defined design space. Overall stability and passivity of the parametric reduced order model are guaranteed by an efficient and reliable combination of traditional passivity-preserving model order reduction methods and interpolation schemes based on a class of positive interpolation operators. A pertinent numerical example validates the proposed parameterized model order reduction approach.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133112780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Step response sensitivity to selected parameters of VLSI inverter — interconnect -inverter system VLSI逆变器-互连器-逆变器系统对所选参数的阶跃响应灵敏度
2010 IEEE 14th Workshop on Signal Propagation on Interconnects Pub Date : 2010-05-09 DOI: 10.1109/SPI.2010.5483548
A. Wardzinska, W. Bandurski
{"title":"Step response sensitivity to selected parameters of VLSI inverter — interconnect -inverter system","authors":"A. Wardzinska, W. Bandurski","doi":"10.1109/SPI.2010.5483548","DOIUrl":"https://doi.org/10.1109/SPI.2010.5483548","url":null,"abstract":"In the paper sensitivity of the voltage step response of the system inverter-interconnect-inverter with respect to selected parameters is considered. The sensitivity coefficients for normalized parameters α, β, ε are given. These formulas are the same as formulas for sensitivity coefficients to R, R<sub>s</sub>, C<sub>0</sub>. Moreover voltage step response deviation to relative parameter α, β, ε variations are estimated.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134589989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reliable bounds for the propagation delay in VLSI nano interconnects based on Multi Wall Carbon Nano Tubes 基于多壁碳纳米管的VLSI纳米互连中传输延迟的可靠边界
2010 IEEE 14th Workshop on Signal Propagation on Interconnects Pub Date : 2010-05-09 DOI: 10.1109/SPI.2010.5483545
B. de Vivo, P. Lamberti, G. Spinelli, V. Tucci
{"title":"Reliable bounds for the propagation delay in VLSI nano interconnects based on Multi Wall Carbon Nano Tubes","authors":"B. de Vivo, P. Lamberti, G. Spinelli, V. Tucci","doi":"10.1109/SPI.2010.5483545","DOIUrl":"https://doi.org/10.1109/SPI.2010.5483545","url":null,"abstract":"The upper and lower bounds of the time-delay due to the variations of some physical and geometrical characteristics of a nano-interconnect based on Multi Wall CNTs, suitable for the 32 and 22nm technology, are evaluated. Interval Analysis is used to define the ranges of the of the p.u.l. parameters of a Transmission Line modeling the interconnect. The Vertex Analysis is then exploited on the parameter space to obtain in a reliable way the time-delay bounding without extensive and costly simulation burden. The obtained results are compared with those of scaled down copper-based structures.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133264857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Nodal order reduction via bilinear conformal transformation 利用双线性保角变换降低节点阶数
2010 IEEE 14th Workshop on Signal Propagation on Interconnects Pub Date : 2010-05-09 DOI: 10.1109/SPI.2010.5483569
Madhavan Swaminathan, Madhavan Swaminathan
{"title":"Nodal order reduction via bilinear conformal transformation","authors":"Madhavan Swaminathan, Madhavan Swaminathan","doi":"10.1109/SPI.2010.5483569","DOIUrl":"https://doi.org/10.1109/SPI.2010.5483569","url":null,"abstract":"A model order reduction process for second order systems is presented. The nodal form of electrical network governing equations is modified through a bilinear conformal transformation in the Laplace domain. Model order reduction of the transformed second order system is carried out through congruent transformation, thus preserving passivity and reciprocity of the system. Proof of concept is shown through examples of power-ground structures.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125703197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Measurement of on-chip transmission-line with stacked split-ring resonators 片上传输线的堆叠分环谐振器测量
2010 IEEE 14th Workshop on Signal Propagation on Interconnects Pub Date : 2010-05-09 DOI: 10.1109/SPI.2010.5483544
A. Tsuchiya, H. Onodera
{"title":"Measurement of on-chip transmission-line with stacked split-ring resonators","authors":"A. Tsuchiya, H. Onodera","doi":"10.1109/SPI.2010.5483544","DOIUrl":"https://doi.org/10.1109/SPI.2010.5483544","url":null,"abstract":"This paper reports measurement results of on-chip transmission-line with split-ring resonators. Split-ring resonator (SRR) has attracted attention as an implementation of metamaterial (left-handed material). However when simple SRR is implemented in LSIs, the resonance frequency becomes around 200GHz and it is too high to employ on on-chip circuits. We designed a stacked SRR to lower the resonant frequency in a 0.18μm CMOS. Measurement results show that the stacked SRRs can realize the resonance frequency below 50GHz. Also measurement results show a guideline of area effective implementation of on-chip SRR.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"16 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125784807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling of chip-package resonance in power distribution networks by an impulse response 基于脉冲响应的配电网芯片封装谐振建模
2010 IEEE 14th Workshop on Signal Propagation on Interconnects Pub Date : 2010-05-09 DOI: 10.1109/SPI.2010.5483595
Y. Uematsu, H. Osaka, M. Yagyu, T. Saito
{"title":"Modeling of chip-package resonance in power distribution networks by an impulse response","authors":"Y. Uematsu, H. Osaka, M. Yagyu, T. Saito","doi":"10.1109/SPI.2010.5483595","DOIUrl":"https://doi.org/10.1109/SPI.2010.5483595","url":null,"abstract":"This paper proposes a method for modeling chip-package resonance using impulse response. To extract chip and package electrical circuit parameters, we assume a circuit equivalent to the loop from the chip to the package decoupling capacitor as the RL-RC parallel circuit and convert it into an RLC parallel circuit. We apply this method to devise an electrical circuit model capable of expressing chip-package resonance with high accuracy, as confirmed by experimental results.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124071335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
HF performance characterization and prediction of 2D redistribution layer interconnects in a 3D-integrated circuit stack 三维集成电路堆叠中二维重分布层互连的高频性能表征与预测
2010 IEEE 14th Workshop on Signal Propagation on Interconnects Pub Date : 2010-05-09 DOI: 10.1109/SPI.2010.5483577
J. Roullard, S. Capraro, T. Lacrevaz, L. Cadix, E. Eid, A. Farcy, B. Fléchet
{"title":"HF performance characterization and prediction of 2D redistribution layer interconnects in a 3D-integrated circuit stack","authors":"J. Roullard, S. Capraro, T. Lacrevaz, L. Cadix, E. Eid, A. Farcy, B. Fléchet","doi":"10.1109/SPI.2010.5483577","DOIUrl":"https://doi.org/10.1109/SPI.2010.5483577","url":null,"abstract":"Effects due to 3D level stack on HF propagation performance of 2D interconnects integrated in the Back End Of Line (BEOL) or realized on the back face of a reported silicon substrate are investigated. The impact of silicon substrate on propagation exponents and delays is pointed out for 2D interconnects used as redistribution lines between stacked chips. In a first part, HF simulation and measurement results are compared to validate electrical models of interconnects. In the second part, a parametric study is performed in order to predict and optimize performances of 2D interconnects for different processes of 3D stacking.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115525713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Passive delay-based macromodels for Signal Integrity verification of multi-chip links 基于无源延迟的多芯片链路信号完整性验证宏模型
2010 IEEE 14th Workshop on Signal Propagation on Interconnects Pub Date : 2010-05-09 DOI: 10.1109/SPI.2010.5483553
A. Chinea, P. Triverio, S. Grivet-Talocia
{"title":"Passive delay-based macromodels for Signal Integrity verification of multi-chip links","authors":"A. Chinea, P. Triverio, S. Grivet-Talocia","doi":"10.1109/SPI.2010.5483553","DOIUrl":"https://doi.org/10.1109/SPI.2010.5483553","url":null,"abstract":"This paper presents a general strategy for the electrical performance assessment of electrically long multi-chip links. A black-box time-domain macromodel is first derived from tabulated frequency responses in scattering form. This model is structured as a combination of ideal delay terms with frequency-dependent rational coefficients. Two passivity enforcement schemes are then presented, enabling safe and reliable transient simulations of the multi-chip link with a standard circuit solver, including nonlinear drivers and receivers.","PeriodicalId":293987,"journal":{"name":"2010 IEEE 14th Workshop on Signal Propagation on Interconnects","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126605052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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