Passive delay-based macromodels for Signal Integrity verification of multi-chip links

Abstract

This paper presents a general strategy for the electrical performance assessment of electrically long multi-chip links. A black-box time-domain macromodel is first derived from tabulated frequency responses in scattering form. This model is structured as a combination of ideal delay terms with frequency-dependent rational coefficients. Two passivity enforcement schemes are then presented, enabling safe and reliable transient simulations of the multi-chip link with a standard circuit solver, including nonlinear drivers and receivers.