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2022 IEEE 4th International Conference on Circuits and Systems (ICCS)最新文献

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Fast Turn Restriction Algorithm to Build Deadlock-Free Modular Chiplet Integration Systems 构建无死锁模块集成系统的快速转弯约束算法
2022 IEEE 4th International Conference on Circuits and Systems (ICCS) Pub Date : 2022-09-23 DOI: 10.1109/ICCS56666.2022.9936469
Wenxu Cao, Shuyan Jiang, Letian Huang
{"title":"Fast Turn Restriction Algorithm to Build Deadlock-Free Modular Chiplet Integration Systems","authors":"Wenxu Cao, Shuyan Jiang, Letian Huang","doi":"10.1109/ICCS56666.2022.9936469","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936469","url":null,"abstract":"To ensure the modularity of the chiplet integration systems while realizing deadlock-free of the networks, the method of modular turn restriction (MTR) was proposed, which aims to find the optimal boundary turn restriction solution to break the loops in the channel dependency graph (CDG). However, the turn restriction algorithm (TRA) in MTR induces huge time complexity, making the optimal solution under large networks extremely hard to find. This paper proposes the fast turn restriction algorithm (FTRA), a method to reduce the time complexity of TRA from $gt O(16^{M-1}$) to O(M2). FTRA aims to find the locally optimal solution through a subspace of the full solution space of TRA by setting constraints on the property of the feasible solutions. An experiment of the algorithms for a $4times 4$ mesh network shows that FTRA can reduce the execution time of TRA by 2 to more than 4 orders of magnitude, specifically, from 2.8 hours to 440 ms. The cycle-accurate simulation of a chiplet integration system composed of five $4times4$ mesh networks shows that the optimal solutions of FTRA achieve very close or even equal network performance to those of TRA.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122981774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Effective Routability-Driven Packing Algorithm for Large-Scale Heterogeneous FPGAs 大规模异构fpga中一种有效的可达性驱动封装算法
2022 IEEE 4th International Conference on Circuits and Systems (ICCS) Pub Date : 2022-09-23 DOI: 10.1109/ICCS56666.2022.9936463
Zijun Li, Yangjie Mei, Jingwen Lin, Ziran Zhu
{"title":"An Effective Routability-Driven Packing Algorithm for Large-Scale Heterogeneous FPGAs","authors":"Zijun Li, Yangjie Mei, Jingwen Lin, Ziran Zhu","doi":"10.1109/ICCS56666.2022.9936463","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936463","url":null,"abstract":"As the increasing complexity and scale of FPGA architecture grows, heterogeneity and routability have greatly challenged FPGA placement. In this paper, we propose an effective routability-driven packing algorithm for large-scale heterogeneous FPGAs. First, we present a novel BLE packing method to deal with the complex clock constraints, meanwhile forming more HCLB-friendly BLEs. Then, we propose a congestion-aware HCLB packing technique to produce placement-friendly netlists without degrading routability. Finally, we adopt an effective and accurate method to perform routing congestion estimation to guide the packing algorithm. Based on the ISPD 2017 benchmarks, experimental results show that our algorithm achieves the best overall routed wirelength and outperforms three state-of-the-art FPGA placers by 9.8%, 8.2%, and 3.4% on routed wirelength, respectively.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126559963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.28-nW 1.97-kHz Relaxation Oscillator for Ultra-Low Power System 用于超低功耗系统的1.28-nW 1.97 khz弛豫振荡器
2022 IEEE 4th International Conference on Circuits and Systems (ICCS) Pub Date : 2022-09-23 DOI: 10.1109/ICCS56666.2022.9936292
Xiaoyuan Wu, Yao Xiao, C. Shi, Leilei Huang, Guangsheng Chen, Runxi Zhang
{"title":"A 1.28-nW 1.97-kHz Relaxation Oscillator for Ultra-Low Power System","authors":"Xiaoyuan Wu, Yao Xiao, C. Shi, Leilei Huang, Guangsheng Chen, Runxi Zhang","doi":"10.1109/ICCS56666.2022.9936292","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936292","url":null,"abstract":"This paper presents a fully integrated 1.97 kHz relaxation oscillator (RXO) based on the 40 nm CMOS process. The RXO is powered by 0. 4V to directly generate a dual phase clock signal with a duty of 50% and the power consumption of only 1. 2SnW, which is suitable for ultra-low-power circuit systems. A proportional-to-absolute-temperature compensation and a complementary-to-absolute-temperature compensation technique are implemented to achieve the temperature stability of output frequency. By adding an enable (EN) signal, the stability of the feedback network can be improved without extra power consumption. The temperature coefficient (TC) of RXO is 170 ppm/°C in the temperature range of −20°C to 80°C. The RXO achieves a Figure of merit (FoM) of 0.649 nW/kHz at room temperature, and its supply voltage coefficient is ± 2.7%/V from 0.4 V to 1.6 V.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131415055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Local Positive Feedback Loop-Reused Technique for Enhancing Performance of Folded Cascode Amplifier 提高折叠级联放大器性能的局部正反馈环复用技术
2022 IEEE 4th International Conference on Circuits and Systems (ICCS) Pub Date : 2022-09-23 DOI: 10.1109/ICCS56666.2022.9936572
Zhang Yu, Zhao Xiao, Dong Liyuan
{"title":"A Local Positive Feedback Loop-Reused Technique for Enhancing Performance of Folded Cascode Amplifier","authors":"Zhang Yu, Zhao Xiao, Dong Liyuan","doi":"10.1109/ICCS56666.2022.9936572","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936572","url":null,"abstract":"A current-reused folded cascode operational transconductance amplifier (OTA) using a local positive feedback (LPFB) technique has been proposed in previous literature, which does not achieve maximum unity gain-bandwidth (GBW). Besides, the stability of LPFB in the LPFB OTA is limited by local common mode feedback (LCMFB) resistors. Based on the analysis, a local positive feedback loop-reused (LPFBR) technique is proposed to improve the performance of conventional LPFB OTA. For a fair comparison, both conventional and proposed OTAs working at saturation region are designed and simulated in SMIC 0.18 μm process. The simulated results demonstrate that the proposed LPFBR OTA has almost 10.5 times the bandwidth and maintains stability compared to that of the conventional LPFB OTA under the condition that LCMFB resistors are increased by a factor of 10.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127705889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research and Design of 1700V 250A SiC MOSFET Driver 1700V 250A SiC MOSFET驱动器的研究与设计
2022 IEEE 4th International Conference on Circuits and Systems (ICCS) Pub Date : 2022-09-23 DOI: 10.1109/ICCS56666.2022.9936209
Wujun Yao, Niu Libo, Wang Dongwen, Sun Pengyun
{"title":"Research and Design of 1700V 250A SiC MOSFET Driver","authors":"Wujun Yao, Niu Libo, Wang Dongwen, Sun Pengyun","doi":"10.1109/ICCS56666.2022.9936209","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936209","url":null,"abstract":"In this paper, RoHM BSM250D17P2E004 as the driving object, the driver and protection circuit of 1700V and 250A SiC MOSFET are studied and designed. The minimum pulse width suppression and anti-crosstalk drive circuit, desaturation detection and active clamp protection circuit of SiC MOSFET are studied emphatically. The reliability of the driving circuit and the validity of the protection circuit are verified by experiments.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115811357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Modular Cascadable 77 GHz Radar System with High Range Resolution 高距离分辨率模块化可级联77 GHz雷达系统
2022 IEEE 4th International Conference on Circuits and Systems (ICCS) Pub Date : 2022-09-23 DOI: 10.1109/ICCS56666.2022.9936222
Shiliang Pu, Lin Shen, Lin Shen, Tong Qian, Tingjun Li, Wang Yan, Haining Yang, Meili She
{"title":"A Modular Cascadable 77 GHz Radar System with High Range Resolution","authors":"Shiliang Pu, Lin Shen, Lin Shen, Tong Qian, Tingjun Li, Wang Yan, Haining Yang, Meili She","doi":"10.1109/ICCS56666.2022.9936222","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936222","url":null,"abstract":"The continuous expansion of urbanization has led to increasingly complex application scenarios for modern urbanized traffic monitoring systems. If many fine objects such as pedestrians, roadblocks and other non-motorized targets are to be distinguished, traditional single vision sensors can no longer be adapted, and a strong demand for high-resolution millimeter wave radar has been put forward. In this paper, we propose a modular 77 GHz radar system based on Texas Instruments AWR2243 radar chip, which can allow the combination of multiple modules and can achieve a longer detection range. We describe the coherent synchronization, synchronous triggering, selected antenna orientation map and the design of the whole system. Finally we show the operating performance of the whole system by some experimental measurements.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125953324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Area-Efficient Deblocking Filter Architecture for Multi-standard Video Codec 一种适用于多标准视频编解码器的区域高效分块滤波器结构
2022 IEEE 4th International Conference on Circuits and Systems (ICCS) Pub Date : 2022-09-23 DOI: 10.1109/ICCS56666.2022.9936221
Sirui Li, Leilei Huang, Xiankui Xiong, Dong Xu, Xuanpeng Zhu, Yibo Fan
{"title":"An Area-Efficient Deblocking Filter Architecture for Multi-standard Video Codec","authors":"Sirui Li, Leilei Huang, Xiankui Xiong, Dong Xu, Xuanpeng Zhu, Yibo Fan","doi":"10.1109/ICCS56666.2022.9936221","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936221","url":null,"abstract":"Video needs to be compressed before transmission or storage, and the continuous development of video coding standards has brought about the need for multi-standard video codecs. Deblocking filter is an important tool to improve the efficiency of video coding in both the H.264 Advanced Video Coding (H.264/AVC) standard and the High Efficiency Video Coding (HEVC) standard. To support these two standards, this paper proposes an area-efficient general deblocking filter hardware architecture. The proposed architecture reuses similar parts in the filter to control the increased area cost of supporting multiple standards and achieves a 37% gate count reduction. And by switching the connection form of filter modules between series and parallel, a good trade-off is made between throughput and area. The architecture has a throughput of 8K@60fps in H.264/AVC and 8K@160fps in HEVC. The experimental result shows that the multi-standard architecture consumes 61.3k gates at 526 MHz in GF 28 nm process, and the design has been successfully integrated into a multi-standard video codec.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127627300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Output Capacitor-Less Low Dropout Regulator Based on Push-Pull Amplifier 一种基于推挽放大器的无输出电容低差稳压器
2022 IEEE 4th International Conference on Circuits and Systems (ICCS) Pub Date : 2022-09-23 DOI: 10.1109/ICCS56666.2022.9936275
Qian Ren, Xiaodie Luo, Yifan Li, Ruyi Liu, Qilong Tang, Min Song
{"title":"An Output Capacitor-Less Low Dropout Regulator Based on Push-Pull Amplifier","authors":"Qian Ren, Xiaodie Luo, Yifan Li, Ruyi Liu, Qilong Tang, Min Song","doi":"10.1109/ICCS56666.2022.9936275","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936275","url":null,"abstract":"In this paper, a fast transient response output capacitor-less low dropout (OCL-LDO) regulator with low quiescent current is presented. A current-mode common-gate differential transconductance amplifier is paired with a push-pull output stage to achieve high slew rate at low quiescent currents. Coupling capacitors are embedded to provide feedback paths to get rid of the limit of bypass bandwidth and a pair of common-mode feedback resistors are used to adjust the dynamic current to improve the transient response performance of the error amplifier. The proposed OCL-LDO is implemented in CMOS 180 nm process, the power supply ranges from 2.5 to 4 V and achieves a stable 1.8 V output over a load range of 0.2-10 mA. The simulation results show that under the maximum load current change, the output voltage spike at 100 ps edge time is less than 340 mV, the settling time is 2.2 us, and the measured quiescent current consumption is 9.25 uA.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121638380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Drift Speed Adaptive Memristor SPICE Model Implementation and Applications in Logic Circuits 漂移速度自适应忆阻器SPICE模型的实现及其在逻辑电路中的应用
2022 IEEE 4th International Conference on Circuits and Systems (ICCS) Pub Date : 2022-09-23 DOI: 10.1109/ICCS56666.2022.9936317
Genglei Zhu, Zefeng Zhang, Wenya Li, Lilian Huang
{"title":"Drift Speed Adaptive Memristor SPICE Model Implementation and Applications in Logic Circuits","authors":"Genglei Zhu, Zefeng Zhang, Wenya Li, Lilian Huang","doi":"10.1109/ICCS56666.2022.9936317","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936317","url":null,"abstract":"This paper presents a drift velocity adaptive memristor SPICE model, which can match different kinds of physical memristor equipment and experimental memristor data by adjusting its own parameters. Mathematical model of a novel memristor device is first introduced in this paper, then four different memristor devices are matched by adjusting parameters of the proposed memristor with maximum average error is only 6.24%. This model is flexible, highly functional and accurate, it can show all the behaviors of resistance random access memory (RRAM), which plays a crucial role in memory and logic design. In addition, we use the two proposed memristor models connected anti-serially to capture an ideal I-V relationship of complementary resistive switch (CRS). Finally, comprehensive comparison and discussion between the model proposed and the existing models from several different levels are carried out. The results prove that the model has potential application in memory and logic design.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126807053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Inrush Current Suppression Circuit with Discharge Function for Airborne DC Power Supply 具有放电功能的机载直流电源涌流抑制电路
2022 IEEE 4th International Conference on Circuits and Systems (ICCS) Pub Date : 2022-09-23 DOI: 10.1109/ICCS56666.2022.9936504
Wen Wang, Lunbo Deng, Guohua Zhou, Jianming Lv
{"title":"Inrush Current Suppression Circuit with Discharge Function for Airborne DC Power Supply","authors":"Wen Wang, Lunbo Deng, Guohua Zhou, Jianming Lv","doi":"10.1109/ICCS56666.2022.9936504","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936504","url":null,"abstract":"High-capacity bulk capacitors are necessarily set at the input terminal of power electronics equipment to meet the electromagnetic compatibility (EMC) test. However, there is an inrush current flowing the bulk capacitor during equipment startup, which is likely to trigger protection of running equipment. In this paper, the requirements of start-up inrush current in relevant standards for airborne DC power supply are introduced, and several methods of inrush current suppression are compared. Two kinds of inrush current suppression circuits based on MOSFET are introduced and their advantages and disadvantages are analyzed in detail. In order to solve the failure problem of inrush current suppression function during hot startup, an improved suppression circuit with shutdown discharge function is proposed. The circuit can timely discharge the gate voltage of the MOSFET when the input voltage drops below the threshold, which has the advantages of low loss and high reliability. Finally, the feasibility of the circuit is verified by software simulations and experiments.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125638017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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