2022 IEEE 4th International Conference on Circuits and Systems (ICCS)最新文献

{"title":"An Ultra-Wideband Spectrum and Spatial Spectrum Sensing System Based on Improved Nyquist Folding Receiver and Phase Coding","authors":"Kailun Tian, Kaili Jiang, Ying Xiong, B. Tang","doi":"10.1109/ICCS56666.2022.9936180","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936180","url":null,"abstract":"In the complex electromagnetic environment, non-cooperative radar signal information extraction and equipment miniaturization in the wide frequency band and wide spatial range are important research topics for radar warning. Some scholars have proposed a high-resolution phase sampling interferometry named Optimum Symmetrical Number System (OSNS). This structure has the characteristics of high resolution, small baseline, a smaller number of phase sampling comparators, and can overcome the Direction of Arrival (DOA) ambiguity caused by the imperfect array spacing, but this algorithm needs to obtain the signal frequency first. To sense the signal frequency in a wide frequency range, a sensor structure, Nyquist folded receiver (NYFR), is proposed, which can receive the signal using a low-speed ADC while retaining the signal information. The architecture introduces a key parameter, the Nyquist zone Index (NZI), which marks the frequency band where the signal originally resides. Direct estimation of NZI requires high signal-to-noise ratio (SNR) conditions and needs to update the algorithm logic according to the signal type. This paper presents an ultra-wideband spectrum and spatial spectrum sensing system based on improved Nyquist folding receiver and phase coding, namely Phase Coding Nyquist Folding Receiver (PC-NYFR). The system combines frequency measurement and direction finding with pre-operation, and NYFR is improved to Dual-antenna Dual-channel NYFR (DDNYFR), which completes effective, high-precision, and anti-noise frequency estimation, compared with the original structure, the performance of SNR requirement is decreased by 3dB; The obtained frequency information is used to encode the phase of DOA like OSNS and complete DOA estimation. PCNYFR is a small baseline array architecture with an ultra-wideband frequency range and wide spatial range, which can obtain all signal information, and uses a small number of antennas, phase comparators, and low-speed ADC. Comparative simulation experiments verify the effectiveness of PC-NYFR and its robustness to noise.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115236490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ReaLSE: Reconfigurable Lightweight Security Engines for Trusted Edge Devices","authors":"Mohamed El-Hadedy, Xinfei Guo","doi":"10.1109/ICCS56666.2022.9936234","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936234","url":null,"abstract":"Security has become a serious threat for IoT devices running on the edge. While IoT chips are usually subject to numerous constraints such as power, form factor, cost and more. The budget for on-chip security engines is very limited. A worldwide competition was launched by NIST to define lightweight cryptographic (LWC) primitives for securing tiny devices. So far, the final round of the LWC competition consists of ten candidates’ submissions that can be categorized as substitution box (Sbox)-based and add-rotate-xor (ARX)-based. The former heavily involves memory accessibility, while the latter involves heavy computations such as additions and rotations. While one can design customized accelerator for each LWC cipher, it lacks generality and involves huge design effort. In the meanwhile, a full reconfigurable system will incur hardware overheads in terms of area and power. Inspired by domain-specific architecture, we propose a series of compact security engine architectures called Reconfigurable Lightweight Security Engines (ReaLSE), that are coupled with some levels of reconfigurability such as different word sizes, different encryption/decryption processes or even different security levels. By striking a balance between flexibility and hardware cost, our proposed designs were able to integrate micro-architectural level optimizations that are specific to certain LWC ciphers while supporting various modes. This new design family increases the availability and adaptability of embedded LWC engines for IoT. We will present various such reconfigurable designs including both ARX and S-boxed based ciphers. Architecture details along with hardware implementation results will also be discussed.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122668960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Heart Sound Diagnosis Processing Unit Based on LSTM Neural Network","authors":"Weixin Zhou, Ang Wang, Lina Yu, Wan'ang Xiao","doi":"10.1109/ICCS56666.2022.9936094","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936094","url":null,"abstract":"Cardiovascular disease is the deadliest disease in the world, so prevention and diagnosis of cardiovascular disease are essential. Manual auscultation cannot meet the demand for heart sound auscultation, and computer automatic heart sound diagnosis offers a new method. In recent years, wearable auscultation devices are receiving increasing attention. However, the low power consumption and high-performance requirements limit wearable device development. In this work, an LSTM-based (Long Short-Term Memory) low-power heart sound diagnostic processing unit (HSDPU) is proposed. Considering the differences between the actual heart sounds and the open-source heart sound dataset, we develop an FPGA system for heart sound acquisition. Data augmentation is used to extend the dataset in response to the imbalance between the collected dataset and the open-source dataset. We develop the heart sound diagnosis system and achieve an accuracy of 96.9%. Then the hardware implementation of the HSDPU is finished and verified by RTL simulation. Finally, we develop the FPGA prototype verification and layout design of the HSDPU. The post-simulation results show that the power consumption of the HSDPU is $289mumathrm{W}$.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"343 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123351337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High Precision RC Relaxation Oscillator for Wide Supply Voltage Swing from 2.5V to 5.5V","authors":"Zena Zhang, Mei Jiang, Feilong Cao","doi":"10.1109/ICCS56666.2022.9936428","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936428","url":null,"abstract":"A low-temperature drift current-mode relaxation oscillator suitable for wide supply voltage swing is presented. The characteristic that the delay of the buffer is proportional to the supply voltage and inversely proportional to the bias current is exploited. The bias of the buffer is provided by the current source that changes with the supply voltage, so as to achieve the purpose that the delay of the buffer is weakly correlated with the supply voltage and suppress the change of the output frequency. A temperature-dependent resistance is used to balance the delay of the buffer with temperature. The experimental results show that the typical frequency of the oscillator is 2MHz. The frequency variation is 0.33%/V for the supply voltage of 2. 5~5.5V and 40.6ppm/°C for temperature of −40~125°C.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127968253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and Design of a X-Band Analog Phase Shifter for Passive Millimeter-Wave Imaging Application","authors":"Jianhao Gong, Wangdong He, Anyong Hu, Julia H. Miao, Xi Chen","doi":"10.1109/ICCS56666.2022.9936197","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936197","url":null,"abstract":"The analysis, design and measurement of a Monolithic Microwave Integrated Circuit (MMIC) analog phase shifter is implemented based on 0.15 $mu$m GaAs pHEMT process. We propose a flexible methodology for phase shifter design which utilizes multistage cascaded phase shifting sections. The equivalent circuit model of the GaAs pHEMT diode is established and the characteristic of the phase shifting section is analyzed. By adjusting the characteristic of the phase shifting section and selecting appropriate number of stages, desired overall performance of the phase shifter is obtained, including over 100° phase shift range, low and nearly constant insertion loss during phase shifting and excellent phase stability when input signal power varies. A single control voltage is required for the chip and the DC consumption is almost zero. This phase shifter has a compact chip size of $1.65 mm times 1.1$ mm which is suitable for high-integrated phased arrays in passive millimeter-wave imaging.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134548309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 12 nA Ultra-Low Quiescent Current Capacitor-Less LDO with 350 ns Fast Transient Response","authors":"Nixiao Yan, Xin Zhang, C. Shi, Leilei Huang, Guangsheng Chen, Runxi Zhang","doi":"10.1109/ICCS56666.2022.9936586","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936586","url":null,"abstract":"This paper presents an output capacitor-less, dual power transistors low-dropout (LDO) regulator with ultra-low quiescent current in 55 nm CMOS process. The LDO employs an adaptive stage to make the LDO a two-stage topology at light load and a three-stage topology at heavy load. A co-enhanced transient circuit is introduced by adding the extra switching current to improve the slew rate without any quiescent current. The simulated results show that the LDO with a quiescent current of 12 nA and a power supply range from 2.5 to 3.6 V achieves a stable 1.2 V output. When the load current changes in steps of $10 mu mathrm{A} -20$ mA with a rise time and a fall time of 200 ns, the LDO can recover within 350 ns and 490 ns.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131593504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Application of Ultrasonic Technology in the Teaching of Signal Analysis and Processing","authors":"Na Li, Haitao Li, L. Ming, Yantong Lu","doi":"10.1109/ICCS56666.2022.9936408","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936408","url":null,"abstract":"Under the background of new engineering, aiming at the problem that the theory and practice of signal analysis and processing teaching in engineering are divorced, taking the calculation of signal correlation as an example, combined with the scientific research results of ultrasonic ranging, this paper deeply explores the innovation of signal analysis and processing teaching mode, and puts forward a new teaching mode of signal analysis and processing based on the integration of science and education, which provides a new idea for the reform of signal analysis and processing teaching mode in new engineering. Teaching practice has proved that the concept of scientific research and education can inject new vitality into classroom teaching, stimulate students’ enthusiasm for learning, and achieve the teaching purpose of applying what they have learned.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129618263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Two-Stage Dynamic Comparator with a PMOS Intermediate Stage","authors":"Xinyu Wang, Jiangbo Wei, Jianhang Yang, Maliang Liu","doi":"10.1109/ICCS56666.2022.9936348","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936348","url":null,"abstract":"This paper introduces a two-stage dynamic comparator which uses a PMOS intermediate stage to provide an extra amplification for the input and reduce the impact of kick-back noise. Benefiting from the pre-amplifier and latch-type comparator, it provides a rail to rail output, achieves a delay time of 66. 2Sps under a differential input of 10mV and consumes 616$mu$W power. This comparator can achieve a working frequency up to 4GHz and 2.1mV offset with an active area of 420 $mu mathrm{m}^{2}$ in 65nm CMOS process.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127457050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 65nm 110GOPS 8T-SRAM Computing-in-Memory Macro with Single Cycle Serial Input Mechanism","authors":"Shumeng Li, Tianqi Xu, Fukun Su, Xian Tang, Yupeng Chen","doi":"10.1109/ICCS56666.2022.9936324","DOIUrl":"https://doi.org/10.1109/ICCS56666.2022.9936324","url":null,"abstract":"This paper presents a high-speed 8T-SRAM computing-in-memory (CIM) macro, which adopts a novel single cycle serial input (SCSI) mechanism and a matching weighted capacitor register circuit, achieving excellent input linearity and calculation speed without input DACs. The register capacitor arrays can be reused by the output SAR ADCs as their four most significant bits (MSBs) DAC capacitors, further improving the area efficiency. The 4kb 8T-SRAM macro supports 4-bit input, 4-bit weight, and 6-bit output, it executes 16 columns of $4btimes 4b$ MAC in parallel, achieving peak throughput of 110.1 GOPS and energy efficiency of 31.4 TOPS/W in 65nm CMOS process.","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125412957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ICCS 2022 Cover Page","authors":"","doi":"10.1109/iccs56666.2022.9936391","DOIUrl":"https://doi.org/10.1109/iccs56666.2022.9936391","url":null,"abstract":"","PeriodicalId":293477,"journal":{"name":"2022 IEEE 4th International Conference on Circuits and Systems (ICCS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134180741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}