A Two-Stage Dynamic Comparator with a PMOS Intermediate Stage

Abstract

This paper introduces a two-stage dynamic comparator which uses a PMOS intermediate stage to provide an extra amplification for the input and reduce the impact of kick-back noise. Benefiting from the pre-amplifier and latch-type comparator, it provides a rail to rail output, achieves a delay time of 66. 2Sps under a differential input of 10mV and consumes 616$\mu$W power. This comparator can achieve a working frequency up to 4GHz and 2.1mV offset with an active area of 420 $\mu \mathrm{m}^{2}$ in 65nm CMOS process.