A 12 nA Ultra-Low Quiescent Current Capacitor-Less LDO with 350 ns Fast Transient Response

Abstract

This paper presents an output capacitor-less, dual power transistors low-dropout (LDO) regulator with ultra-low quiescent current in 55 nm CMOS process. The LDO employs an adaptive stage to make the LDO a two-stage topology at light load and a three-stage topology at heavy load. A co-enhanced transient circuit is introduced by adding the extra switching current to improve the slew rate without any quiescent current. The simulated results show that the LDO with a quiescent current of 12 nA and a power supply range from 2.5 to 3.6 V achieves a stable 1.2 V output. When the load current changes in steps of $10 \mu \mathrm{A} -20$ mA with a rise time and a fall time of 200 ns, the LDO can recover within 350 ns and 490 ns.