Fast Turn Restriction Algorithm to Build Deadlock-Free Modular Chiplet Integration Systems

Abstract

To ensure the modularity of the chiplet integration systems while realizing deadlock-free of the networks, the method of modular turn restriction (MTR) was proposed, which aims to find the optimal boundary turn restriction solution to break the loops in the channel dependency graph (CDG). However, the turn restriction algorithm (TRA) in MTR induces huge time complexity, making the optimal solution under large networks extremely hard to find. This paper proposes the fast turn restriction algorithm (FTRA), a method to reduce the time complexity of TRA from $\gt O(16^{M-1}$) to O(M2). FTRA aims to find the locally optimal solution through a subspace of the full solution space of TRA by setting constraints on the property of the feasible solutions. An experiment of the algorithms for a $4\times 4$ mesh network shows that FTRA can reduce the execution time of TRA by 2 to more than 4 orders of magnitude, specifically, from 2.8 hours to 440 ms. The cycle-accurate simulation of a chiplet integration system composed of five $4\times4$ mesh networks shows that the optimal solutions of FTRA achieve very close or even equal network performance to those of TRA.