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1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

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A NMOS 64K static RAM 一个NMOS 64K静态RAM
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156360
A. Ebel, G. Atwood, E. So, S. Liu, V. Kynett, R. Jecmen, J. Mingo, Haiping Dun
{"title":"A NMOS 64K static RAM","authors":"A. Ebel, G. Atwood, E. So, S. Liu, V. Kynett, R. Jecmen, J. Mingo, Haiping Dun","doi":"10.1109/ISSCC.1982.1156360","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156360","url":null,"abstract":"A 50ns 8K×8 static RAM developed with a double-poly/ scaled NMOS technology will be reported. The RAM memory cell is 0.5 mil<sup>2</sup>resulting in a 64K die size of 54756 mil<sup>2</sup>.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114978430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A recombination model for the low current performance of submicron devices 亚微米器件低电流性能的重组模型
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156422
R. Lefferts, R. Swan, J. Meindl
{"title":"A recombination model for the low current performance of submicron devices","authors":"R. Lefferts, R. Swan, J. Meindl","doi":"10.1109/ISSCC.1982.1156422","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156422","url":null,"abstract":"This paper will cover a generation-recombination model which describes the influence of metallic precipitates on the current gain, leakage current, and 1/f noise of small geometry transistors. The model predicts an increase in device sensitivity to contamination as geometries are reduced to submicron dimensions.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115768270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Is there life after 64K 64K之后还有生命吗
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156392
R. Foss
{"title":"Is there life after 64K","authors":"R. Foss","doi":"10.1109/ISSCC.1982.1156392","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156392","url":null,"abstract":"Each new generation of DRAMs has been found to require increasing need for time to transfer the initial set of operational components to large volume production. Several years is now the norm for the current generation of 64Ks. What are the factors which give rise to this phenomenon and what are the implications in the trends for the future . . . It is clear that there are many diverse approaches in architecture, circuits and processes, and also user requirements diverging from the standard functional specifications. One now questions which way industry will go. On a long term basis, it is possible that the DRAMs,as presently structured, are approaching fundamental limits and will be superceded. If this is so, what will we have as a successor... Panelists will discuss these topics and project roads that may be taken.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116654502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 40ns CMOS E2PROM 40ns CMOS E2PROM
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156402
R. Stewart, D. Plus
{"title":"A 40ns CMOS E2PROM","authors":"R. Stewart, D. Plus","doi":"10.1109/ISSCC.1982.1156402","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156402","url":null,"abstract":"This Paper will report on an 8K CMOS/SOS E2PROM with an access time of 38ns at 5V, 60mW power dissipation and write voltage as low as 12V.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122436997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An ECL compatible 4K CMOS RAM 一个ECL兼容的4K CMOS RAM
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156338
E. Hudson, S. Smith
{"title":"An ECL compatible 4K CMOS RAM","authors":"E. Hudson, S. Smith","doi":"10.1109/ISSCC.1982.1156338","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156338","url":null,"abstract":"This paper will discuss a 4K×1 ECL compatible static RAM using a HMOSII/CMOS process and speed-optimized CMOS circuits. Input and output levels have been found to meet specifications of the ECL 10K logic family. Address access time is 20ns and current drain is 150mA under nominal conditions.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"423 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114058056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Echo canceller for a 80kbs baseband modem 用于80kbs基带调制解调器的回声消除器
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156421
O. Agazzi, D. Hodges, D. Messerschmitt, W. Lattin
{"title":"Echo canceller for a 80kbs baseband modem","authors":"O. Agazzi, D. Hodges, D. Messerschmitt, W. Lattin","doi":"10.1109/ISSCC.1982.1156421","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156421","url":null,"abstract":"A 16-tap adaptive transversal filter to provide 50dB echo suppression at 80Kb, fabricated in NMOS, will be described. Analog and digital techniques have been employed to reduce element accuracy and die area requirements for LSI realization.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121196902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 64Kb CMOS RAM 64Kb CMOS RAM
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156311
S. Konishi, J. Matsunaga, T. Ohtani, M. Sekine, M. Isobe, T. Iizuka, Y. Uchida, S. Kohyama
{"title":"A 64Kb CMOS RAM","authors":"S. Konishi, J. Matsunaga, T. Ohtani, M. Sekine, M. Isobe, T. Iizuka, Y. Uchida, S. Kohyama","doi":"10.1109/ISSCC.1982.1156311","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156311","url":null,"abstract":"This report will cover the design of a fault-tolerant 8K×8b static RAM using a double polysilicon CMOS technology. Memory access is 70ns typically, while consuming 15mW operating power and 10μW standby power.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121699330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Redundancy in RAMs ram中的冗余
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156306
T. Rodgers
{"title":"Redundancy in RAMs","authors":"T. Rodgers","doi":"10.1109/ISSCC.1982.1156306","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156306","url":null,"abstract":"Virtually everyone agrees that the 200%-2000% yield improvement offered by redundancy makes its acceptance a necessity for the economic viability of RAM manufacturers. But, there is considerable controversy over important short-term issues: Should the 64K DRAM have redundancy? Should fuses be programmed by electrical or laser pulses? Will redundancy have an adverse effect on testability and/or reliability? . . . These and related issues will be assessed by the panelists.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114852358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 5W microwave pulsed oscillator using power GaAs FETs 功率GaAs场效应管的5W微波脉冲振荡器
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156337
N. Furutani, Y. Arai
{"title":"A 5W microwave pulsed oscillator using power GaAs FETs","authors":"N. Furutani, Y. Arai","doi":"10.1109/ISSCC.1982.1156337","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156337","url":null,"abstract":"A 5w oscillator with a 20ns burstwidth at 4.3GHz, applicable for radio altimeters, will be discussed.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122276231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2µ CMOS/LSI 32-point fast fourier transform processor 一个2 & # 181;CMOS/LSI 32点快速傅立叶变换处理器
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156346
B. Troutman, G. McIver, W. Kingsley, B. Whalen
{"title":"A 2&#181; CMOS/LSI 32-point fast fourier transform processor","authors":"B. Troutman, G. McIver, W. Kingsley, B. Whalen","doi":"10.1109/ISSCC.1982.1156346","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156346","url":null,"abstract":"A monolithic 2μ CMOS/LSI processor, operating on 32 complex data samples and computing 32 complete Fourier coefficients, will be described. The transform is implemented using the in-place radix decimation-in-time algorithm.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121768601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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