S. Konishi, J. Matsunaga, T. Ohtani, M. Sekine, M. Isobe, T. Iizuka, Y. Uchida, S. Kohyama
{"title":"64Kb CMOS RAM","authors":"S. Konishi, J. Matsunaga, T. Ohtani, M. Sekine, M. Isobe, T. Iizuka, Y. Uchida, S. Kohyama","doi":"10.1109/ISSCC.1982.1156311","DOIUrl":null,"url":null,"abstract":"This report will cover the design of a fault-tolerant 8K×8b static RAM using a double polysilicon CMOS technology. Memory access is 70ns typically, while consuming 15mW operating power and 10μW standby power.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"31","resultStr":"{\"title\":\"A 64Kb CMOS RAM\",\"authors\":\"S. Konishi, J. Matsunaga, T. Ohtani, M. Sekine, M. Isobe, T. Iizuka, Y. Uchida, S. Kohyama\",\"doi\":\"10.1109/ISSCC.1982.1156311\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This report will cover the design of a fault-tolerant 8K×8b static RAM using a double polysilicon CMOS technology. Memory access is 70ns typically, while consuming 15mW operating power and 10μW standby power.\",\"PeriodicalId\":291836,\"journal\":{\"name\":\"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"31\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1982.1156311\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1982.1156311","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This report will cover the design of a fault-tolerant 8K×8b static RAM using a double polysilicon CMOS technology. Memory access is 70ns typically, while consuming 15mW operating power and 10μW standby power.
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