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2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)最新文献

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Towards the Monolithic Integration of III-V Compound Semiconductors on Si: Selective Area Growth in High Aspect Ratio Structures vs. Strain Relaxed Buffer-Mediated Epitaxy III-V型化合物半导体在硅上的单片集成:高宽高比结构的选择性面积生长与应变松弛缓冲介导外延
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340064
M. Cantoro, C. Merckling, S. Jiang, W. Guo, N. Waldron, H. Bender, A. Moussa, B. Douhard, W. Vandervorst, M. Heyns, J. Dekoster, R. Loo, M. Caymax
{"title":"Towards the Monolithic Integration of III-V Compound Semiconductors on Si: Selective Area Growth in High Aspect Ratio Structures vs. Strain Relaxed Buffer-Mediated Epitaxy","authors":"M. Cantoro, C. Merckling, S. Jiang, W. Guo, N. Waldron, H. Bender, A. Moussa, B. Douhard, W. Vandervorst, M. Heyns, J. Dekoster, R. Loo, M. Caymax","doi":"10.1109/CSICS.2012.6340064","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340064","url":null,"abstract":"We report two approaches to integrate high quality III-V templates by epitaxial growth with low defectivity on Si wafers. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagation from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132856500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Device Scale Heat Removal for High Power Density GaN Devices 高功率密度氮化镓器件的器件级散热
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340114
A. Bhunia, A. Brackley, C. Nguyen, B. Brar
{"title":"Device Scale Heat Removal for High Power Density GaN Devices","authors":"A. Bhunia, A. Brackley, C. Nguyen, B. Brar","doi":"10.1109/CSICS.2012.6340114","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340114","url":null,"abstract":"Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) are thermally limited much below the electrical capability of the devices. The unique challenge of a GaN HEMT is its ultra-high heat flux at the micro-scale gate fingers. The traditional packaging and base plate level liquid cooling have limited capability and is far from the heat source, resulting in high thermal resistance from the device junction to the coolant, and ultimately limiting the RF power. We present a device-level high heat flux cooling solution with liquid micro-jet impingement within ~100 μm distance of the heat source. A preliminary demonstration of the technique on a GaN-on-Silicon device shows 50% higher heat dissipation capability, compared to the state-of-the-art pin fin base plate liquid cooling, while maintaining the device junction temperature at 150°C. If the dissipation power level is held constant at 35 W of dissipation power, the technique reduces the device junction temperature by 45°C.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116145124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 22.4 dBm Two-Way Wilkinson Power-Combined Q-Band SiGe Class-E Power Amplifier with 23% Peak PAE 22.4 dBm双向Wilkinson功率组合q波段SiGe类功率放大器，峰值PAE为23%
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340076
K. Datta, J. Roderick, H. Hashemi
{"title":"A 22.4 dBm Two-Way Wilkinson Power-Combined Q-Band SiGe Class-E Power Amplifier with 23% Peak PAE","authors":"K. Datta, J. Roderick, H. Hashemi","doi":"10.1109/CSICS.2012.6340076","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340076","url":null,"abstract":"A Q-band two-stage Class-E power amplifier is designed and fabricated in a 0.13 μm SiGe HBT BiCMOS process. A low-loss wide-band two-way Wilkinson power combiner is used for on-chip power dividing and combining at the input and output of the design. A mm-wave layout-aware class-E design procedure has been followed to enable efficient switching mode operation of the power amplifier in the Q-band. Stabilization networks and subharmonic terminations have been included to prevent the occurrence of unwanted impact ionization-induced negative base current and even/odd mode oscillation in the power-combined design. The fabricated chip shows a measured performance of 22.4 dBm output power at 23% peak power added efficiency (PAE), and 9 dB power gain across 4 GHz centered around 45 GHz for a supply voltage of 2.5 V. The total chip area including the pads is 1.1 mm × 2.2 mm.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125211233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Degradation Characteristics of High-Voltage AlGaN/GaN-on-Si Heterostructure FETs under DC Stress 高压AlGaN/GaN-on-Si异质结构场效应管在直流应力下的降解特性
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340103
Shinhyuk Choi, Jae-Gil Lee, H. Yoon, H. Cha, Hyungtak Kim
{"title":"Degradation Characteristics of High-Voltage AlGaN/GaN-on-Si Heterostructure FETs under DC Stress","authors":"Shinhyuk Choi, Jae-Gil Lee, H. Yoon, H. Cha, Hyungtak Kim","doi":"10.1109/CSICS.2012.6340103","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340103","url":null,"abstract":"We have fabricated field-plated AlGaN/GaN Heterostructure Field Effect Transistors(HFETs) on Si substrate for high voltage operation and submitted the devices to the DC stress tests to investigate the degradation phenomena. The devices were stressed under two different types of bias configuration including on-state with high current and off-state with low current. Several degradation characteristics such as the reduction of on-current, the increase of gate leakage, and the decrease of transconductance were identified. The degradation showed the moderate dependence on the field plate dimensional parameters and TCAD simulation indicated that this dependence was attributed to the electric field distribution in the channel.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131764867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
S-Band Class-F Power Amplifier with Integrated Switched Mode Power Supply 带集成开关电源的s波段f类功率放大器
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340071
G. van der Bent, P. de Hek, S. Geurts, H. Brouzes, F. V. van Vliet
{"title":"S-Band Class-F Power Amplifier with Integrated Switched Mode Power Supply","authors":"G. van der Bent, P. de Hek, S. Geurts, H. Brouzes, F. V. van Vliet","doi":"10.1109/CSICS.2012.6340071","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340071","url":null,"abstract":"An S-band radar transmitter MMIC is reported containing a class-F power amplifier and a switched mode power supply. The integration of the power supply offers the possibility to optimize the power amplifier bias voltage for each individual device in a AESA antenna. This has several advantages such as amplitude tapering with preservation of efficiency, the reduction of spurious signals due to decoherence and the removal of single point of failure.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114831876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Planar Switchable Capacitor with Embedded Two-Dimensional Electron System for Higher Integrations in VLSI and RFIC 面向VLSI和RFIC高集成度的嵌入式二维电子系统的平面可切换电容器
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340074
P. Dianat, R. Prusak, F. Quaranta, A. Cola, B. Nabet
{"title":"A Planar Switchable Capacitor with Embedded Two-Dimensional Electron System for Higher Integrations in VLSI and RFIC","authors":"P. Dianat, R. Prusak, F. Quaranta, A. Cola, B. Nabet","doi":"10.1109/CSICS.2012.6340074","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340074","url":null,"abstract":"A metal-semiconductor-metal capacitor with embedded two-dimensional charge is designed and fabricated. Capacitance-Voltage characteristics exhibit switchability with a large voltage sensitivity. Maximum and minimum capacitances outperform previous predictions with potential applicability in RFICs and VLSI for reducing the cross-talk among transmission lines and achievement of higher integrations. The device can replace bulky conductors with its negative capacitance feature. The large light sensitivity in the C-V makes this capacitor an ideal candidate for monolithic microwave-photonic integrated circuits.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"365 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123406064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Linearization of a Spatially-Combined X-Band 100-W GaAs FET Power Amplifier System with Predistortion Linearizer 带预失真线性化器的空间组合x波段100-W GaAs FET功率放大器系统的线性化
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340066
Y. Chung, B. Deckman, M. DeLisio
{"title":"Linearization of a Spatially-Combined X-Band 100-W GaAs FET Power Amplifier System with Predistortion Linearizer","authors":"Y. Chung, B. Deckman, M. DeLisio","doi":"10.1109/CSICS.2012.6340066","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340066","url":null,"abstract":"This paper presents the design and performance of an X-band GaAs FET power amplifier (PA) system with 100-W of saturated output power. A simple and cost-effective predistortion linearizer is developed to increase the linear output power of the PA system. To spatially combine output powers of GaAs FETs and to launch output signals directly into the WR-112 waveguide, the PA uses a pair of microstrip-to-coaxial transition probes. Measurement shows that linearization significantly reduces the PA's nonlinear signal distortions, resulting in a 3 dB increase of operating linear output power.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122376121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
SiGe BiCMOS Technologies for Applications above 100 GHz 适用于100ghz以上应用的SiGe BiCMOS技术
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340061
H. Rücker, B. Heinemann, A. Fox
{"title":"SiGe BiCMOS Technologies for Applications above 100 GHz","authors":"H. Rücker, B. Heinemann, A. Fox","doi":"10.1109/CSICS.2012.6340061","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340061","url":null,"abstract":"This paper describes recent advances in SiGe HBT technology. Technological developments introduced for improved radio-frequency performance are discussed. HBT device characteristics are presented for a 0.13 μm SiGe BiCMOS technology with fT/fmax of 300/500 GHz and mini-mum CML ring oscillator gate delays of 2.0 ps. Sample circuit applications for operating frequencies above 100 GHz are discussed.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116504250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Novel Electrostatic Discharge (ESD) Protection Circuit in D-Mode pHEMT Technology d模pHEMT技术中一种新型静电放电保护电路
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340079
Q. Cui, Shuyun Zhang, Yibing Zhao, Bin Hou, J. Liou
{"title":"A Novel Electrostatic Discharge (ESD) Protection Circuit in D-Mode pHEMT Technology","authors":"Q. Cui, Shuyun Zhang, Yibing Zhao, Bin Hou, J. Liou","doi":"10.1109/CSICS.2012.6340079","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340079","url":null,"abstract":"Electrostatic discharge (ESD) protection structures in the D-Mode GaAs HEMT technology are commonly constructed using either stacked Schottky diode or Single-Gate clamp. This paper develops an improved ESD protection clamp based on a novel multi-gate pHEMT in D-Mode technology. With similar layout area, the proposed ESD protection clamp can carry much higher current than the conventional single-gate pHEMT clamp under the human body model (HBM) stress.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126785702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A K-Band 5W Doherty Amplifier MMIC Utilizing 0.15µm GaN on SiC HEMT Technology 基于0.15µm GaN和SiC HEMT技术的k波段5W多赫蒂放大器MMIC
2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2012-10-25 DOI: 10.1109/CSICS.2012.6340057
C. Campbell, K. Tran, M. Kao, S. Nayak
{"title":"A K-Band 5W Doherty Amplifier MMIC Utilizing 0.15µm GaN on SiC HEMT Technology","authors":"C. Campbell, K. Tran, M. Kao, S. Nayak","doi":"10.1109/CSICS.2012.6340057","DOIUrl":"https://doi.org/10.1109/CSICS.2012.6340057","url":null,"abstract":"The design and performance of a K-Band Doherty amplifier MMIC is presented. The monolithic 2-stage amplifier was fabricated with a dual field plate 0.15um GaN on SiC HEMT process technology. Measured continuous wave results at 23GHz demonstrate over 5W of saturated output power and up to 48% power added efficiency. Peak efficiency occurs at approximately 1dB of gain compression and the amplifier maintains 25% power added efficiency at 8dB of input power back off from P1dB.","PeriodicalId":290079,"journal":{"name":"2012 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"368 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125696595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 69
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