{"title":"A high throughput CMP process by using an Epic ECR directional ion source for intermetal dielectric","authors":"J.K. Wang","doi":"10.1109/ICSICT.1995.500072","DOIUrl":"https://doi.org/10.1109/ICSICT.1995.500072","url":null,"abstract":"Wafer fabrication technology is rapidly advancing toward four or five layers of metallization with geometries of 0.35 /spl mu/m and smaller, aspect ratios of 3:1, and a requirement that the intermetal dielectric be globally planarized. Epic's ECR Directional Ion Source combined with in situ sputter etch has been demonstrated repeatedly to fill 3:1 high aspect ratio gaps at 0.25 /spl mu/m gap widths. The superior silane-based oxide does not absorb moisture over an extended period of time. The void-free gap fill in IMD provides the foundation for CMP because no slurry will be left in the IMD to cause reliability problems. The simultaneous deposition and etch step enhance the build-up of IMD over the lower valley on the device wafers. Thus IMD deposited by Epic exhibits a better planarity on the deposited wafer. The wafer topography after ECR deposition exhibits a unique surface that has only small peaks and step structures. These structures are easily removed by the CMP process. The increase in CMP throughput can be over 33%. The shortened polishing time helps the stability and repeatability of the CMP process.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121198400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"National technology roadmaps: the U.S. semiconductor experience","authors":"W. Spencer, T. Seidel","doi":"10.1109/ICSICT.1995.500069","DOIUrl":"https://doi.org/10.1109/ICSICT.1995.500069","url":null,"abstract":"Behind the projection for the technology for the next 15 years are complete roadmaps for each of the major technologies in support of the manufacture of silicon integrated circuits. This work was the result of hundreds of scientists and engineers from universities, industry, and government working together to develop a set of industry requirements for silicon technology. The history of this roadmap process, the methods used to develop the National Technology Roadmap for Semiconductors, some of the overall requirements of the Roadmap, and finally, some suggestions for international cooperation and roadmaps in other technologies are the subject of this paper.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114239950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VHdbx: an X window system based high-level debugger for the VHDL simulation environment","authors":"B. Wan, Jinian Bian","doi":"10.1109/ICSICT.1995.500165","DOIUrl":"https://doi.org/10.1109/ICSICT.1995.500165","url":null,"abstract":"In this paper we present a graphical high-level debugger for the VHDL simulation environment. The features of the tool are its user friendly interface based on Motif under X Window system, a capability to high-level debugging, a capability to support many methods to set breakpoints, selective enabling and disabling of breakpoints, single stepping and trace mode, a capability to display source code, simulation results, and graphical views such as schematic diagram and design hierarchical diagram synchronically, a capability to view the current values of signals or variables and change them, a capability of visualization of simulation results, and a capability to view the waveform of results while simulating.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114350413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Du, X. Gu, X.F. Huang, J. Zhou, K. Chen, H. Chen, J.H. Yang, B.C. Cao
{"title":"Hydrogenated amorphous silicon PIN photodiode for optically addressed spatial light modulators","authors":"J. Du, X. Gu, X.F. Huang, J. Zhou, K. Chen, H. Chen, J.H. Yang, B.C. Cao","doi":"10.1109/ICSICT.1995.503543","DOIUrl":"https://doi.org/10.1109/ICSICT.1995.503543","url":null,"abstract":"An optically addressed spatial light modulator (OASLM) with a photoreceptor and a liquid crystal is one of the key components in optical information processing systems and displays. In this paper we describe the preparation and operating characteristics of an OASLM which uses hydrogenated amorphous silicon (a-Si:H) as the photoreceptor, and twisted nematic liquid crystal (TNLC) as the electro-optic modulating material. Based on the characteristics of our OASLM, the function of real-time optical logic operation have been performed.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116218887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaodong Huang, P. Han, Youdou Zheng, Liqun Hu, R. Wang, Shunming Zhu
{"title":"Low-temperature epitaxy of phosphorus doped Si and Si/sub 1-x/Ge/sub x/ films by RTP/VLP-CVD","authors":"Xiaodong Huang, P. Han, Youdou Zheng, Liqun Hu, R. Wang, Shunming Zhu","doi":"10.1109/ICSICT.1995.500242","DOIUrl":"https://doi.org/10.1109/ICSICT.1995.500242","url":null,"abstract":"In situ phosphorus doped Si and Si/sub 1-x/Ge/sub x/ epitaxial layers have been grown at 600/spl deg/C in a very low pressure chemical vapor deposition system using SiH/sub 4/ and 1800 ppm PH/sub 3/ diluted in H/sub 2/. The epitaxial growth rates were found to decrease with phosphorus doping and input of the diluent H/sub 2/. The constant phosphorus concentration with depth for a steady flow of PH/sub 3/ was achieved. Dopant concentration is a function of gas phase dopant concentration. Chemical concentrations as high as 2.5/spl times/10/sup 20/ P/cm/sup 3/ were obtained in Si epitaxial layers. The doping level can be modulated between 1.2/spl times/10/sup 20/ and 1.5/spl times/10/sup 17/ P/cm/sup 3/. There is no evidence of a time-dependent accumulation of phosphorus on the growth surface or the reactor wall.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116296597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HREM analysis of ultra-thin oxides","authors":"R. Sinclair, M. Niwa, T. Kouzaki","doi":"10.1109/ICSICT.1995.503545","DOIUrl":"https://doi.org/10.1109/ICSICT.1995.503545","url":null,"abstract":"Ultra-thin SiO/sub 2/ layers on Si (e.g., sub-10 nm) will be increasingly important in future VLSI devices. Precise control of thickness and interface roughness are important parameters. High resolution electron microscopy (HREM) is extremely effective for characterizing such features, as is illustrated here for gate oxides and tunneling oxides.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"1283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116488221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Kuo, T. Toms, M. Weidner, H. Choe, D. Shum, Ko-Min Chang, P. Smith
{"title":"A microcontroller with 100 K bytes embedded flash EEPROM","authors":"C. Kuo, T. Toms, M. Weidner, H. Choe, D. Shum, Ko-Min Chang, P. Smith","doi":"10.1109/ICSICT.1995.499653","DOIUrl":"https://doi.org/10.1109/ICSICT.1995.499653","url":null,"abstract":"As application of microcontrollers to achieve a cost effective system solution becomes more pervasive, demands for higher performance and higher functional integration continue to increase for microcontrollers. Flash EEPROM with its electrical reprogrammability and high density, when integrated on chip, can provide a microcontroller with enhanced performance and versatility, and offer a more cost effective system solution. This paper presents the development of a 16 bit microcontroller with 100 Kbytes of embedded flash EEPROM, that includes a block erasable flash EEPROM module. Using the SCSG (Source-Coupled Split-Gate) flash EEPROM cell, the embedded flash memory has achieved a typical program time of 20 /spl mu/s and erase time of 20 ms. The device operates at frequency of over 25 MHz. For embedded applications, the criteria for selecting a flash EEPROM cell are different from those for a stand alone flash memory. For stand alone memory, small cell area is often the most critical factor to be considered. For embedded applications, low overall production cost of the microcontrollers with integrated flash EEPROM is often the primary concern. For this reason, a robust flash EEPROM cell that is compatible with the existing host logic process without added tight process controls is a key criterion for use in embedded applications.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127603163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. K. Han, M. Bhat, D. Wristers, H. Wang, D. Kwong
{"title":"Recent developments in N/sub 2/O/NO-based ultra thin oxynitride gate dielectrics for CMOS ULSI applications","authors":"L. K. Han, M. Bhat, D. Wristers, H. Wang, D. Kwong","doi":"10.1109/ICSICT.1995.499277","DOIUrl":"https://doi.org/10.1109/ICSICT.1995.499277","url":null,"abstract":"This paper reviews recent developments in N/sub 2/O- and NO-based oxynitride gate dielectrics for CMOS ULSI applications. These dielectrics are extremely attractive due to their process simplicity, thickness controllability, and excellent electrical characteristics. In this paper, several issues like thickness scaling, growth kinetics, chemical composition, electrical properties, hot-carrier reliability, and EEPROM applications of these dielectrics are discussed.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126560454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Flash memories, their status and trends","authors":"F. Masuoka, T. Endoh","doi":"10.1109/ICSICT.1995.499651","DOIUrl":"https://doi.org/10.1109/ICSICT.1995.499651","url":null,"abstract":"Flash memories will stir additional progress in semiconductor memories. While DRAMs play a key role in computer memories, they, cannot replace hard and floppy disks, but flash memories can, so markets for these devices may grow larger than DRAM markets.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126018587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Chen, A.S. Yapsir, S. Wu, R. Schulz, D. Yee, D. Sadana, H. Hovel, T. Ning, G. Shahidi, B. Davari
{"title":"0.25 /spl mu/m low power CMOS devices and circuits from 8 inch SOI materials","authors":"B. Chen, A.S. Yapsir, S. Wu, R. Schulz, D. Yee, D. Sadana, H. Hovel, T. Ning, G. Shahidi, B. Davari","doi":"10.1109/ICSICT.1995.500080","DOIUrl":"https://doi.org/10.1109/ICSICT.1995.500080","url":null,"abstract":"0.25 /spl mu/m SOI-CMOS ring oscillators, various circuits and SRAM from 8-inch SIMOX wafers are reported. Both active power and stand-by leakage are compared on fully integrated lots for both SOI and bulk materials. The great advantage of SOI for active power reduction is demonstrated for various circuits. Stand-by leakage paths have been systematically studied on their dependence on material, process integration and devices. Potential solutions to reduce each stand-by leakage current are discussed. From these early 8-inch SIMOX materials, encouraging results suggest that low stand-by power can be achieved by optimizations of SOI material preparation, process integration and device design.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134393291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}