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Proceedings Euromicro Symposium on Digital Systems Design最新文献

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FPGA based controller for heterogenous image processing system 基于FPGA的异构图像处理系统控制器
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952366
M. Gorgon, J. Przybyło
{"title":"FPGA based controller for heterogenous image processing system","authors":"M. Gorgon, J. Przybyło","doi":"10.1109/DSD.2001.952366","DOIUrl":"https://doi.org/10.1109/DSD.2001.952366","url":null,"abstract":"In the present paper construction of a controller is described, which is used to control the RETINA image processing platform. The 32-bit RETINA card is dedicated to be used for image acquisition, processing and analysis. The module resources include Video ADC, Virtex FPGA device, floating point Motorola 96002 DSP and PCI Master interface, what enables the execution of all the operations in real-time. Controller is the main control centre for the module, supervising the modes and phases of its operation, and it is also used as a arbiter for the module's communication resources.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120988679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Fast test cost calculation for hybrid BIST in digital systems 数字系统中混合BIST测试成本的快速计算
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952315
E. Orasson, Rein Raidma, R. Ubar, G. Jervan, Zebo Peng
{"title":"Fast test cost calculation for hybrid BIST in digital systems","authors":"E. Orasson, Rein Raidma, R. Ubar, G. Jervan, Zebo Peng","doi":"10.1109/DSD.2001.952315","DOIUrl":"https://doi.org/10.1109/DSD.2001.952315","url":null,"abstract":"The paper presents a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored precomputed deterministic test patterns. A procedure is proposed for fast calculation of the cost of hybrid BIST at different lengths of pseudorandom test to find an optimal balance between test sets, and to perform a core test with minimum cost of both time and memory, and without losing test quality. Compared to the previous approach, based on iterative use of deterministic ATPG for evaluating the cost of stored patterns, a new, extremely fast procedure is proposed, which calculates costs on a basis of fault table manipulations. Experiments on the ISCAS benchmark circuits show that the new procedure is about two orders of magnitude faster than the previous one.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128616429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Rotating ultrasonic signal vectors with a word-parallel CORDIC processor 旋转超声信号矢量与字并行CORDIC处理器
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952290
A. Paplinski, Nandita Bhattacharjee, Charles Greif
{"title":"Rotating ultrasonic signal vectors with a word-parallel CORDIC processor","authors":"A. Paplinski, Nandita Bhattacharjee, Charles Greif","doi":"10.1109/DSD.2001.952290","DOIUrl":"https://doi.org/10.1109/DSD.2001.952290","url":null,"abstract":"The CORDIC algorithm is an iterative method for the efficient computation of vector rotations and several other trigonometric and hyperbolic functions. We have developed a fast, redundant, constant-scale factor, word-parallel implementation of a CORDIC algorithm to rotate ultrasonic signal vectors. The implementation is an improvement of a similar 1996 algorithm know as the differential CORDIC. The CORDIC processor is a part of an ultrasonic imaging system under development and has been implemented using logic synthesis of VHDL descriptions on a Xilinx Virtex 800 FPGA. The algorithm has been simulated with MATLAB. The results of simulation and testing of the CORDIC rotator using a novel VHDL testbench have been presented. The error resulting from truncations is well within the expected limit.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129283429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Portable acquisition system for measurements of pressures, temperatures and humidity in lower limb prosthesis 用于测量下肢假体压力、温度和湿度的便携式采集系统
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952334
G. Coldani, G. Danese, R. Gandolfi, P. Ghidetti, F. Leporati, R. Lombardi
{"title":"Portable acquisition system for measurements of pressures, temperatures and humidity in lower limb prosthesis","authors":"G. Coldani, G. Danese, R. Gandolfi, P. Ghidetti, F. Leporati, R. Lombardi","doi":"10.1109/DSD.2001.952334","DOIUrl":"https://doi.org/10.1109/DSD.2001.952334","url":null,"abstract":"An instrument with a DSP for measurements of pressures, temperatures and humidity in lower limb prosthesis is presented. It has got sixteen analog input channels. The signals from the transducers are linked to the input channels and feed the conditioning network which is made up by amplification stages and peak detectors. Input signals are converted into a digital form by a 10 bit analog to digital converter integrated into the DSP and information are pre-processed and then stored in a removable memory with high capacity. The instalment is also equipped with an LCD display to show the progress of the interesting parameters in real time. Now we are testing the instrument at the Prosthetic Center in Vigorso di Budrio (Italy). The aim of these tests is checking the correct operation of the instrument in different working ways and bringing constructive modifications to prosthesis to better locate the sensors.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123515140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Header compression in Handel-C-an Internet application and a new design language handelc是一种Internet应用程序，也是一种新的设计语言
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952110
K. Torkelsson, J. Ditmar
{"title":"Header compression in Handel-C-an Internet application and a new design language","authors":"K. Torkelsson, J. Ditmar","doi":"10.1109/DSD.2001.952110","DOIUrl":"https://doi.org/10.1109/DSD.2001.952110","url":null,"abstract":"In the ESPRIT project \"Software engineering for Hardware Design\", a critical and complex function in the Ericsson IPv6 router RXI820 was designed. The router is optimized for voice transmission in the mobile base station network. IP Header Compression (RFC 2507), compresses and restores long headers of packets in point-to-point message streams improving bandwidth utilization and real-time characteristics. The function was implemented in FPGA technology using a new high-level design language based on the software language ANSI-C. The design method used is similar to methods for software design. The resulting hardware can be tested in full speed on a PCI-board. In a parallel effort, a second group of designers using the same specification implemented the same functionality using traditional hardware design methods and tools. This enabled us to compare the efficiency of the two design methods. Using the new methods, the design was completed 3-4 times faster with similar results in terms of speed and area. This can be attributed to support for sequential logic and a compact representation in the language and to a software-like design methodology with fast turnaround in the design environment.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125303706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Synthesis of conditional behaviors using hierarchical conditional dependency graphs and constraint logic programming 使用分层条件依赖图和约束逻辑规划的条件行为综合
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952285
K. Kuchcinski, C. Wolinski
{"title":"Synthesis of conditional behaviors using hierarchical conditional dependency graphs and constraint logic programming","authors":"K. Kuchcinski, C. Wolinski","doi":"10.1109/DSD.2001.952285","DOIUrl":"https://doi.org/10.1109/DSD.2001.952285","url":null,"abstract":"This paper presents a new high-level synthesis (HLS) approach which addresses the problem of synthesis of conditional behaviors. In proposed methodology, the conditional behaviors are represented by Hierarchical Conditional Dependence Graphs (HCDG) and synthesized using derived Constraints Logic Programming (CLP) models. Our synthesis methods exploit multicycle operations and chaining as well as conditional resource sharing and speculative execution at the same time. These techniques are essential in HLS and the experiments carried out using the developed prototype system showed good performance of the synthesized designs and proved the feasibility of the presented approach.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"62 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120810574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A comparison of five different multiprocessor SoC bus architectures 五种不同的多处理器SoC总线架构的比较
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952283
Kyeong Keol Ryu, Eung S. Shin, V. Mooney
{"title":"A comparison of five different multiprocessor SoC bus architectures","authors":"Kyeong Keol Ryu, Eung S. Shin, V. Mooney","doi":"10.1109/DSD.2001.952283","DOIUrl":"https://doi.org/10.1109/DSD.2001.952283","url":null,"abstract":"The performance of a system, especially multiprocessor system, heavily depends upon the efficiency of its bus architecture. In System-on-a-Chip (SoC), the bus architecture can be devised with advantages such as shorter propagation delay (resulting in a faster bus clock), larger bus width, and multiple buses. This paper presents five different SoC bus architectures for a multiprocessor system: Global Bus I Architecture (GBIA), Global Bus II Architecture (GBIIA), Bi-FIFO Bus Architecture (BFBA), Crossbar Switch Bus Architecture (CSBA), and CoreConnect Bus architecture (CCBA). The performance of these architectures is evaluated using applications from wireless communications-an Orthogonal Frequency Division Multiplexing (OFDM) transmitter-and from video processing-an MPEG2 decoder. To increase performance, these bus architectures employ a pipelined scheme, resulting in improved throughput. While all five bus architectures perform well, we find that BFBA and CSBA perform the best for the OFDM transmitter and the MPEG2 decoder, respectively.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"33 49","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114046887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 102
A run-time support environment for reconfigurable systems 可重构系统的运行时支持环境
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952257
L. Bubb, M. Edwards, P. Green, C. Pimlott, K. Rees, M. Stewart, A. Taylor, M. Vakondios, J. Yates
{"title":"A run-time support environment for reconfigurable systems","authors":"L. Bubb, M. Edwards, P. Green, C. Pimlott, K. Rees, M. Stewart, A. Taylor, M. Vakondios, J. Yates","doi":"10.1109/DSD.2001.952257","DOIUrl":"https://doi.org/10.1109/DSD.2001.952257","url":null,"abstract":"This paper presents a novel FPGA Support System (FSS) that facilitates the execution of hardware-based tasks on a dynamically reconfigurable FPGA. The FSS provides the mechanisms to support the placement, execution and removal of blocks on the FPGA. A key feature of the FSS is its ability to provide communication between concurrently executing hardware blocks and software objects during the run-time of a system. The FSS was initially developed to run on a hardware platform consisting of an ARM7 processor interfaced to a Xilinx 6264 FPGA and a dual-port memory. The design, implementation and current status of the FSS are discussed, together with our initial results based on the implementation of a discrete wavelet transform application.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116357923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An assessment of FPGA suitability for implementation of real-time motion estimation 对FPGA实现实时运动估计的适用性进行评估
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952332
A. Ryszko, K. Wiatr
{"title":"An assessment of FPGA suitability for implementation of real-time motion estimation","authors":"A. Ryszko, K. Wiatr","doi":"10.1109/DSD.2001.952332","DOIUrl":"https://doi.org/10.1109/DSD.2001.952332","url":null,"abstract":"Motion estimation is very computational demanding operation during video compression process, thus special hardware architectures are required to achieve real-time compression performance. Advantages in increasing complexity, density and speed of programmable logic devices will soon allow us to implement this kind of application specific processors within one programmable chip. This paper evaluates the performance of Block Matching hardware architectures implemented in Xilinx FPGA. Systolic arrays for Full Search algorithm inferred by Komarek and Pirsch (1989) have been implemented and evaluated by achieved clock rate and number of occupied FPGA resources. Results show that with 2D type systolic arrays it is possible to achieve real-time performance of motion estimation for CIF images even with moderate capacity (250 k gates) FPGA chip.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126959269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Test strategies on functionally partitioned module-based programmable architecture for base-band processing 基于功能分区模块的基带处理可编程体系结构测试策略
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952317
S. Leung, A. Postula, A. Hemani
{"title":"Test strategies on functionally partitioned module-based programmable architecture for base-band processing","authors":"S. Leung, A. Postula, A. Hemani","doi":"10.1109/DSD.2001.952317","DOIUrl":"https://doi.org/10.1109/DSD.2001.952317","url":null,"abstract":"A specialised reconfigurable architecture for telecommunication base-band processing is augmented with testing resources. The routing network is linked via virtual wire hardware modules to reduce the area occupied by connecting buses. The number of switches within the routing matrices is also minimised, which increases throughput without sacrificing flexibility. The testing algorithm was developed to systematically search for faults in the processing modules and the flexible high-speed routing network within the architecture. The testing algorithm starts by scanning the externally addressable memory space and testing the master controller. The controller then tests every switch in the route-through switch matrix by making loops from the shared memory to each of the switches. The local switch matrix is also tested in the same way. Next the local memory is scanned. Finally, pre-defined test vectors are loaded into local memory to check the processing modules. This algorithm scans all possible paths within the interconnection network exhaustively and reports all faults. Strategies can be inserted to bypass minor faults.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125168737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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