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Proceedings Euromicro Symposium on Digital Systems Design最新文献

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Genetic programming in FPGA implementation of addition as a part of the convolution 遗传编程在FPGA中实现加法作为卷积的一部分
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952370
E. Jamro, K. Wiatr
{"title":"Genetic programming in FPGA implementation of addition as a part of the convolution","authors":"E. Jamro, K. Wiatr","doi":"10.1109/DSD.2001.952370","DOIUrl":"https://doi.org/10.1109/DSD.2001.952370","url":null,"abstract":"In FPGAs, an addition should be carried out in the standard way employing ripple-carry adders (rather than carry-save adders), which complicates search for an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of inputs to the adder block have been considered e.g. correlation between inputs. These parameters are specified in different ways for different convolver architectures. Consequently optimisation of the adder tree is a key issue addressed in this paper. Simulated Annealing and Genetic Programming have been proposed, and obtained results compared with the Greedy Algorithm (GrA) and the Exhaustive Search (ES). As a result, the GrA is the best solution when computation time is of great importance. Otherwise, the Simulated Annealing should be employed for the number of addition inputs N>8, and the ES is recommended for N/spl les/8. Employing the Simulated Annealing gives about 10-20% area reduction in comparison to the GrA.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115256994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
System Modeling in the COSMA Environment COSMA环境中的系统建模
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952264
Wiktor B. Daszczuk, Waldemar Grabski, J. Miescicki, J. Wytrębowicz
{"title":"System Modeling in the COSMA Environment","authors":"Wiktor B. Daszczuk, Waldemar Grabski, J. Miescicki, J. Wytrębowicz","doi":"10.1109/DSD.2001.952264","DOIUrl":"https://doi.org/10.1109/DSD.2001.952264","url":null,"abstract":"The aim of this paper is to demonstrate how the COSMA environment can be used for system modeling. This environment is a set of tools based on Concurrent State Machines paradigm and is developed in the Institute of Computer Science at the Warsaw University of Technology. Our demonstration example is a distributed brake control system dedicated for a railway transport. The paper shortly introduces COSMA. Next it shows how the example model can be validated by our temporal logic analyzer.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"963 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127039451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Synthesis of ASM-based self-checking controllers 基于asm的自检控制器的合成
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952122
I. Levin, V. Sinelnikov, M. Karpovsky
{"title":"Synthesis of ASM-based self-checking controllers","authors":"I. Levin, V. Sinelnikov, M. Karpovsky","doi":"10.1109/DSD.2001.952122","DOIUrl":"https://doi.org/10.1109/DSD.2001.952122","url":null,"abstract":"In this paper we present a new technique for on-line checking of FPGA-based sequential devices defined by their algorithmic state machines (ASMs). The technique utilizes specific properties of ASMs for achieving the totally self-checking goal with a low hardware overhead. This technique is based on the architecture that consists of two portions: a self-checking sequential device and a separate totally self-checking (TSC) checker. Each of these portions is implemented as a combination of an \"evolution\" block and an \"execution\" block. Comparison of code vectors transferred between these blocks provides for the totally self-checking property. The proposed technique does not require any redundant encoding of output words and uses a one-rail design, thereby drastically decreasing the required overhead. The paper presents overhead estimations and results for benchmarks for the proposed architecture.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116286847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
GREEDY IIP: partitioning large graphs by greedy iterative improvement 贪婪IIP:通过贪婪迭代改进划分大图
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952117
B. Becker, T. Eschbach, R. Drechsler, Wolfgang Günther
{"title":"GREEDY IIP: partitioning large graphs by greedy iterative improvement","authors":"B. Becker, T. Eschbach, R. Drechsler, Wolfgang Günther","doi":"10.1109/DSD.2001.952117","DOIUrl":"https://doi.org/10.1109/DSD.2001.952117","url":null,"abstract":"In various areas of computer science and mathematics, including scientific computing, task scheduling and VLSI design, the graph concept is used for modeling purposes, and graph partitioning algorithms are required to obtain solutions. For example, with increasing complexities of circuit design the circuit graphs may have several millions of nodes, while the CAD tools, like e.g. layout or visualization tools, work best on smaller subproblems. Thus, often partitions with a large number of components have to be determined. We present GREEDY IIP, a partitioning algorithm based on a sequence of greedy local operations. These operations are combined in an iterative manner directed by a restricted hill climbing approach. The algorithm is particularly successful, if a large number of final partitions, i.e. more than 1000, has to be computed. Experimental results on a large number of benchmarks are given. In comparison to the state-of-the-art tools GREEDY IIP shows significant advantages with respect to quality, space requirements and in many cases also with respect to run time.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132945124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Applying formal verification with protocol compiler 使用协议编译器进行形式验证
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952270
Christian Stangier, Ulrich Holtmann
{"title":"Applying formal verification with protocol compiler","authors":"Christian Stangier, Ulrich Holtmann","doi":"10.1109/DSD.2001.952270","DOIUrl":"https://doi.org/10.1109/DSD.2001.952270","url":null,"abstract":"This paper presents a practical methodology for the application of formal verification to the industrial design environment \"Protocol Compiler\". Our verification flow is to first create a testbench and simulate the design. Then we modify the testbench and perform a formal verification technique called assertion checking. The examples are taken from the networking arena. The first is a simplified RS232 transceiver, the second a pipelined FIFO-like buffer written in Verilog. We show that assertion checking fits well into the design flow and is easy to use within Protocol Compiler.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122063249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Application of decision-making method for architecture selection of ADSL modem 决策方法在ADSL调制解调器结构选择中的应用
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952113
J. Soininen, S. Boumard, Tommi Salminen, H. Heusala
{"title":"Application of decision-making method for architecture selection of ADSL modem","authors":"J. Soininen, S. Boumard, Tommi Salminen, H. Heusala","doi":"10.1109/DSD.2001.952113","DOIUrl":"https://doi.org/10.1109/DSD.2001.952113","url":null,"abstract":"This paper presents a method for assisting the decision-making of the technologies and architectures of system chips. The method combines functional complexity analyses, reuse of intellectunl property blocks, technology forecasts and functionality-architecture mappings into unifom measure of architecture quality. This figure of quality can be used in rapid comparison of architecture alternatives, without the need of detailed design or specification. The method has been applied to ADSL modem architectures for the comparison of feasibilities. The best architectures found were similar to commercially available ADSL chip sets. The method extends traditional complexity analyses by taking into account improvements in technologies and tools. It reduces the risks involved in strategic decisions at early stages of design, when the essential product characteristics are determined.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128371379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Cork stopper classification using FPGAs and digital image processing techniques 利用fpga和数字图像处理技术对软木塞进行分类
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952295
M. A. Vega-Rodríguez, J. M. Sánchez-Pérez, J. Pulido
{"title":"Cork stopper classification using FPGAs and digital image processing techniques","authors":"M. A. Vega-Rodríguez, J. M. Sánchez-Pérez, J. Pulido","doi":"10.1109/DSD.2001.952295","DOIUrl":"https://doi.org/10.1109/DSD.2001.952295","url":null,"abstract":"In this paper we study the use of FPGAs as part of an industrial inspection system. More exactly, to evaluate the cork stopper quality applying real-time image processing. Our system uses the HOT2-XL PCI board, a hardware module library implementing some of the most common operations for image processing, and a Visual C++ application in order to validate the hardware designs and manage the platform. Also, we propose an algorithm for obtaining different features of cork stopper defects, so allowing their classification. Finally, the practical results obtained with this algorithm are presented along with the conclusions and future work.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126964568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Minimization of OPKFDDs using genetic algorithms 利用遗传算法最小化opkfdd
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952120
Mi-jin Jung, G. Lee, Sungju Park, R. Drechsler
{"title":"Minimization of OPKFDDs using genetic algorithms","authors":"Mi-jin Jung, G. Lee, Sungju Park, R. Drechsler","doi":"10.1109/DSD.2001.952120","DOIUrl":"https://doi.org/10.1109/DSD.2001.952120","url":null,"abstract":"OPKFDDs (Ordered Pseudo-Kronecker Functional Decision Diagrams) are one of ordered-DDs (Decision Diagrams) in which each node can take one of three decomposition types: Shannon, positive Davio and negative Davio. OPKFDDs provide representations of Boolean functions with smaller number of nodes than other DDs. Since an appropriate decomposition type has to be chosen for each node, the size of the representation is decided by the selection of the decomposition type as well as the variable ordering of the diagram. To overcome the huge search space for an optimal solution, a genetic algorithm is proposed to generate OPKFDDs with the minimal number of nodes with experimental results.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123375719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Regular realization of symmetric functions using reversible logic 使用可逆逻辑的对称函数的规则实现
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952289
M. Perkowski, M. Chrzanowska-Jeske, A. Mishchenko, Xiaoyu Song, A. Al-Rabadi, Barton C. Massey, P. Kerntopf, A. Buller, L. Józwiak, A. Coppola
{"title":"Regular realization of symmetric functions using reversible logic","authors":"M. Perkowski, M. Chrzanowska-Jeske, A. Mishchenko, Xiaoyu Song, A. Al-Rabadi, Barton C. Massey, P. Kerntopf, A. Buller, L. Józwiak, A. Coppola","doi":"10.1109/DSD.2001.952289","DOIUrl":"https://doi.org/10.1109/DSD.2001.952289","url":null,"abstract":"Reversible logic is of increasing importance to many future computer technologies. We introduce a regular structure to realize symmetric functions in binary reversible logic. This structure, called a 2*2 net structure, allows for a more efficient realization of symmetric functions than the methods introduced by the other authors. Our synthesis method allows us to realize arbitrary symmetric function in a completely regular structure of reversible gates with relatively little \"garbage\". Because every Boolean function can be made symmetric by repeating input variables, our method is applicable to arbitrary multi-input multi-output Boolean functions and realizes such arbitrary function in a circuit with a relatively small number of additional gate outputs. The method can also be used in classical logic. Its advantages in terms of numbers of gates and inputs/outputs are especially seen for symmetric or incompletely specified functions with many outputs.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114218665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Effective and efficient FPGA synthesis through functional decomposition based on information relationship measures 通过基于信息关系测度的功能分解实现高效的FPGA综合
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952114
L. Józwiak, A. Chojnacki
{"title":"Effective and efficient FPGA synthesis through functional decomposition based on information relationship measures","authors":"L. Józwiak, A. Chojnacki","doi":"10.1109/DSD.2001.952114","DOIUrl":"https://doi.org/10.1109/DSD.2001.952114","url":null,"abstract":"In this paper, a new information-driven circuit synthesis method is proposed that targets LUT-based FPGAs. The method is based on the bottom-up general functional decomposition and theory of information relationship measures that we previously developed. It differs considerably from all other known methods. The experimental results from the automatic circuit synthesis tool that implements the method clearly demonstrate that functional decomposition based on information relationship measures produces effective FPGA circuits.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116227620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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