Applying formal verification with protocol compiler

Abstract

This paper presents a practical methodology for the application of formal verification to the industrial design environment "Protocol Compiler". Our verification flow is to first create a testbench and simulate the design. Then we modify the testbench and perform a formal verification technique called assertion checking. The examples are taken from the networking arena. The first is a simplified RS232 transceiver, the second a pipelined FIFO-like buffer written in Verilog. We show that assertion checking fits well into the design flow and is easy to use within Protocol Compiler.