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FPGA implementation of addition as a part of the convolution FPGA实现的加法作为卷积的一部分
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952368
E. Jamro, K. Wiatr
{"title":"FPGA implementation of addition as a part of the convolution","authors":"E. Jamro, K. Wiatr","doi":"10.1109/DSD.2001.952368","DOIUrl":"https://doi.org/10.1109/DSD.2001.952368","url":null,"abstract":"Addition is a fundamental operation for the convolution (FIR filters). In FPGAs, addition should be carried out in a standard way employing ripple-carry adders (rather than carry-save adders), which complicates search for an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of inputs to the adders tree have been considered, e.g. correlation between inputs. These parameters are specified in different ways for different convolver architectures: Multiplierless Multiplication, Look-Up Table based Multiplication, Distributed Arithmetic. Furthermore, optimization techniques: Exhaustive Search and Greedy Algorithm have been implemented, and as a result, the Greedy Algorithm is the best solution when time of computation is of great importance. Otherwise, the Exhaustive Search should be employed for the number of the addition inputs n/spl les/8. This paper is a part of the research on the AuToCon-Automated Tool for generating Convolution in FPGAs.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123862806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Level assignment for displaying combinational logic 显示组合逻辑的等级分配
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952262
R. Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst
{"title":"Level assignment for displaying combinational logic","authors":"R. Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst","doi":"10.1109/DSD.2001.952262","DOIUrl":"https://doi.org/10.1109/DSD.2001.952262","url":null,"abstract":"Netlist viewers in VLSI CAD usually display gate-level circuits in a column-oriented style for easy readability. Each gate has to be assigned to one column, called a \"level\" in the following. In this paper we present a level assignment algorithm that finds application in displaying large netlists. The algorithm has polynomial worst case behavior and in contrast to standard depth first search (DFS) methods computes well balanced graphs resulting in improved graphics. A large set of experiments is given to point out the differences between DFS and the new interval algorithm.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122392713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Transistor chaining with integrated dynamic folding for 1-D leaf cell synthesis 具有集成动态折叠的晶体管链用于一维叶细胞合成
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952356
Krzysztof S. Berezowski
{"title":"Transistor chaining with integrated dynamic folding for 1-D leaf cell synthesis","authors":"Krzysztof S. Berezowski","doi":"10.1109/DSD.2001.952356","DOIUrl":"https://doi.org/10.1109/DSD.2001.952356","url":null,"abstract":"In this paper, a new method of transistor chaining for 1-D automatic leaf cell synthesis is presented. The method allows synthesis of cells suitable for row-based layouts with no restrictions imposed on network topologies/transistor sizes. The novelty of the solution arises from transistor chaining with integrated dynamic transistor folding. We provide the theoretical analysis of transistor folding, then formulate the problem and solve it using the computational model made after that of Bar-Yehuda et al. (1989). The model serves us as a basis for the novel algorithm constructed using the dynamic programming technique. The preliminary experiments show that the method reaches good quality chainings and the dynamic folding leads to further elimination of the diffusion gaps comparing to the recent results of other researchers. This results in the reduction of the layout width as well as the improvement of its manufacturability and quality.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"507 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122757025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Synchronizing a high-speed SIMD processor array 同步高速SIMD处理器阵列
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952338
Stefan Lund, L. Bengtsson
{"title":"Synchronizing a high-speed SIMD processor array","authors":"Stefan Lund, L. Bengtsson","doi":"10.1109/DSD.2001.952338","DOIUrl":"https://doi.org/10.1109/DSD.2001.952338","url":null,"abstract":"A synchronization method for a high speed scalable SIMD (Single instruction stream Multiple Data stream) processor array is presented. The method is developed for an architecture using distributed clocking and hierarchical SIMD control. In such an architecture, scalability is radically enhanced by an array-size independent (local) clock skew. This paper focuses on the instruction start synchronization problem inherent in a processor array when using the SIMD node of control and distributed clocking. It is shown how this can be solved in hardware, and bounds on the tolerable skew using this method are presented.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124302273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast and compact sequential circuits through the information-driven circuit synthesis 快速紧凑的顺序电路通过信息驱动电路合成
Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952116
L. Józwiak, A. Chojnacki, A. Slusarczyk
{"title":"Fast and compact sequential circuits through the information-driven circuit synthesis","authors":"L. Józwiak, A. Chojnacki, A. Slusarczyk","doi":"10.1109/DSD.2001.952116","DOIUrl":"https://doi.org/10.1109/DSD.2001.952116","url":null,"abstract":"Modern circuit implementation technologies (FPGAs, CPLDs, complex gates, etc.) introduce new implementation constraints and optimization criteria to sequential circuit synthesis. Moreover, to ensure good quality results, these criteria need to be applied throughout the entire circuit synthesis process, starting at state encoding. In this paper, we present new methods and tools for state encoding and combinational synthesis of sequential circuits based on new criteria of information flow optimization. Together they form a unified and complete pre-placement synthesis chain. Experimental results indicate that the unified, information-driven approach is effective, resulting in circuits from IWLS benchmark being on average 25% smaller and 30% faster than those synthesized by another state-of-the-art tools.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133207673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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