FPGA implementation of addition as a part of the convolution

Abstract

Addition is a fundamental operation for the convolution (FIR filters). In FPGAs, addition should be carried out in a standard way employing ripple-carry adders (rather than carry-save adders), which complicates search for an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of inputs to the adders tree have been considered, e.g. correlation between inputs. These parameters are specified in different ways for different convolver architectures: Multiplierless Multiplication, Look-Up Table based Multiplication, Distributed Arithmetic. Furthermore, optimization techniques: Exhaustive Search and Greedy Algorithm have been implemented, and as a result, the Greedy Algorithm is the best solution when time of computation is of great importance. Otherwise, the Exhaustive Search should be employed for the number of the addition inputs n/spl les/8. This paper is a part of the research on the AuToCon-Automated Tool for generating Convolution in FPGAs.