Proceedings Euromicro Symposium on Digital Systems Design最新文献_第6页

Applying caching to two-level adaptive branch prediction 将缓存应用于两级自适应分支预测

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952280

C. Egan, G. Steven, W. Shim, L. Vintan

{"title":"Applying caching to two-level adaptive branch prediction","authors":"C. Egan, G. Steven, W. Shim, L. Vintan","doi":"10.1109/DSD.2001.952280","DOIUrl":"https://doi.org/10.1109/DSD.2001.952280","url":null,"abstract":"During the 1990s Two-level Adaptive Branch Predictors were developed to meet the requirement for accurate branch prediction in high-performance superscale processors. However, while two-level adaptive predictors achieve very high prediction rates, they tend to be very costly. In particular, the size of the second level Pattern History Table (PHT) increases exponentially as a function of history register length. Furthermore, many of the prediction counters in a PHT are never used; predictions are frequently generated from non-initialised counters and several branches may update the same counter, resulting in interference between branch predictions. In this paper, we propose a Cached Correlated Two-Level Branch Predictor in which the PHT is replaced by a Prediction Cache. Unlike a PHT, the Prediction Cache saves only relevant branch prediction information. Furthermore, predictions are never based on uninitialised entries and interference between branches is eliminated. We simulate three versions of our Cached Correlated Branch Predictors. The first predictor is based on global branch history information while the second is based on local branch history information. The third predictor exploits the ability of cached predictors to combine both global and local history information in a single predictor. We demonstrate that our predictors deliver higher accuracy than conventional predictors at a significantly lower cost.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125510880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Synthesis of sequential circuits on programmable logic devices based on new models of finite state machines 基于有限状态机新模型的可编程逻辑器件顺序电路综合

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952274

S. Valeri

引用次数: 13

Design and implementation of reconfigurable processor for problems of combinatorial computations 组合计算问题可重构处理器的设计与实现

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952250

I. Skliarova, A. Ferrari

引用次数: 16

Two-criterial constraint-driven FSM state encoding for low power 低功耗双准则约束驱动FSM状态编码

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952123

M. Koegst, Steffen Rülke, G. Franke, M. Avedillo

引用次数: 3

Optimisation of PPMC model for hardware implementation 硬件实现的PPMC模型优化

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952251

C. F. Uribe, S. R. Jones

{"title":"Optimisation of PPMC model for hardware implementation","authors":"C. F. Uribe, S. R. Jones","doi":"10.1109/DSD.2001.952251","DOIUrl":"https://doi.org/10.1109/DSD.2001.952251","url":null,"abstract":"The development of new and more powerful applications in data communications and computer systems has required an ever-increasing capacity to handle large amounts of data. Lossless data compression techniques have been developed to exploit further available bandwidth of such systems by reducing the amount of data to transmit or store. They have been implemented in both software and hardware. The former approach provides good compression ratios but presents speed limitations. The latter approach offers the possibility of high-speed compression to suit the most demanding applications. Current available hardware implementations are based mainly on LZ (Lempel-Ziv) class of compression schemes. Experience suggests that classical statistical methods, particularly PPM (Prediction by Partial Matching) class of algorithms, are impractical for being too slow and resource hungry for hardware realisation. However, there seems to have been relatively little work looking at the potential for reorganising and restructuring the algorithm for hardware implementation. This paper presents a version of the PPMC class of algorithms structured for efficient hardware support and analyses the issues of its hardware implementation.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125804809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Timing driven wiring on an advanced microprocessor 高级微处理器上的时序驱动线路

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952352

P. Kartschoke, S. Geissler

引用次数: 0

Pipelined genetic architecture with fitness on the fly 流水线遗传结构与适应性在飞行

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952340

Aitor Ibarra, J. Lanchares, J. Hidalgo, F. Saenz

引用次数: 1

Hierarchical modeling and verification of embedded systems 嵌入式系统的分层建模与验证

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952119

L. Cortés, P. Eles, Zebo Peng

引用次数: 17

Synchronizing low-cost energy aware sensors in a short-range wireless cell 在短距离无线蜂窝中同步低成本的能量感知传感器

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952362

M. Nordman, W. Kozlowski, O. Vähämäki

引用次数: 4

Combining languages in embedded system design 结合语言进行嵌入式系统设计

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952118

R. Ernst

引用次数: 0