{"title":"Reconfigurable computing at Xilinx","authors":"S. Guccione","doi":"10.1109/DSD.2001.952124","DOIUrl":"https://doi.org/10.1109/DSD.2001.952124","url":null,"abstract":"Summary form only givem, as follows. In the last decade and a half, Field Programmable Gate Arrays (FPGAs) have grown from simple devices with a few hundred programmable logic gates to densities beyond one million gates. This growth in density has led to an ever-expanding area of application for these devices. From their early use as simple interface or \"glue\" logic, FPGAs have moved on to become popular platforms for implementing system bus interfaces, including industry standards such as PCI. As device density has surpassed one million gates, FPGA co-processing in data-intensive applications such as Digital Signal Processing (DSP) and networking has become commonplace. The recent announcement of the Virtex II FPGA+CPU device from Xilinx, as well as similar announcements from other vendors, indicate that the trend toward single chip FPGA+CPU processing will continue. And with ten million gate devices under development, it is expected that more system functionality, including more general purpose processing, will continue to migrate into the FPGA. While much of this type of coprocessing can also be accomplished with fixed Application Specific Integrated Circuit (ASIC) hardware, the ability to reprogram FPGA devices, even in system, opens up new opportunities for system design. Reconfigurable logic provides new methods for increasing performance, decreasing power consumption and increasing system functionality. Along with these new benefits come challenges, particularly in the area of software design tools. Tools such as Xilinx's JBits point the way toward providing a single unified environment for programming CPUs, configuring and reconfiguring hardware resources and providing integrated debug support for the single chip reconfigurable systems of the future.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131223744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Test generation and fault simulation methods on the basis of cubic algebra for digital devices","authors":"V. Hahanov, A. Babich","doi":"10.1109/DSD.2001.952286","DOIUrl":"https://doi.org/10.1109/DSD.2001.952286","url":null,"abstract":"Models and methods of digital circuit analysis for test generation and fault simulation are offered. The two-frame cubic algebra for compact description of sequential primitive element (here and further, primitive) in the form of cubic coverings is used. It is used for digital circuit designing, fault simulation and fault-free simulation as well. Problems of digital circuit testing are formulated as linear equations. The described cubic fault simulation method allows to propagate primitive fault lists from its inputs to outputs; to generate analytical equations for deductive fault simulation of digital circuit at gate, functional and algorithmic description levels; to build comparative and interpretative fault simulators for digital circuit. The fault list cubic coverings (FLCC), which allow to create single sensitization paths, are proposed. The test generation method for single stuck-at fault (SSF) detection with usage of FLCC is developed.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132191766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Architectural design of a fast floating-point multiplication-add fused unit using signed-digit addition","authors":"Chichyang Chen, Liang-An Chen, Jih-Ren Cheng","doi":"10.1109/DSD.2001.952324","DOIUrl":"https://doi.org/10.1109/DSD.2001.952324","url":null,"abstract":"Signed digit (SD) addition is applied to the design of a new floating-point (FLP) multiplication-add fused (MAF) unit. This adoption, together with the proposed two-step normalization method, can reduce the three-word-length addition that is required in the conventional FLP MAF unit to two-word-length addition. Furthermore, sign reversion of the intermediate mantissa that requires three-word-length carry propagation in the conventional MAF unit is replaced by only single-word sign detection. These two improvements can enhance the speed and cost of the MAF unit significantly. With the use of the SD addition, the circuit of the unit can be designed in a more regular and simple manner, which is a property that is desired in VLSI design. The proposed FLP MAF unit has been designed and simulated by using Verilog hardware description language. The functions of the designed unit are verified to be correct.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117285760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An improved input-output encoding approach for functional decomposition","authors":"M. Venkatesan","doi":"10.1109/DSD.2001.952260","DOIUrl":"https://doi.org/10.1109/DSD.2001.952260","url":null,"abstract":"Functional decomposition is a process of representing a complex function as a function of smaller functions. The size of the decomposed and the number of don't cares it contains is determined during the encoding process. This work proposes a novel input-output encoding approach that minimizes the size of both decomposed function and introduces additional don't cares in the decomposed functions. The weighted graph approach heuristically determines the optimal encoding. The approach has been implemented and tested using the MCNC benchmarks and the decomposed functions are optimal.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122212675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An approach to minimization of decision diagrams","authors":"P. Kerntopf","doi":"10.1109/DSD.2001.952121","DOIUrl":"https://doi.org/10.1109/DSD.2001.952121","url":null,"abstract":"One of the most promising concepts which has been developed for efficient representation functions is Linearly Transformed Binary Decision Diagram (LTBDD). We present extensions to LTBDDs called Function-driven Decision Diagrams (fDDs). The notion of fDDs is based on using simple balanced (including nonlinear) Boolean functions for defining transformations of decision diagrams. In this context a new scheme of preprocessing which corresponds to inverse transformations as well as using composition of transformations are very efficient for minimization of fDDs. The first experimental results show that fDDs driven by nonlinear Boolean functions can be more compact than LTBDDs, with a reasonable cost. Further extensions of fDDs are also mentioned such as Function-driven Kronecker Functional Decision Diagrams and Multiple-Valued Function-driven Decision Diagrams.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114068242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Rawski, Rafal Rzechowski, Z. Jachna, I. Brzozowski
{"title":"Practical aspects of logic synthesis based on functional decomposition","authors":"M. Rawski, Rafal Rzechowski, Z. Jachna, I. Brzozowski","doi":"10.1109/DSD.2001.952115","DOIUrl":"https://doi.org/10.1109/DSD.2001.952115","url":null,"abstract":"General functional decomposition has important applications in many fields of modern engineering and science. However, it is mainly perceived as a method of logic synthesis for implementation of Boolean functions into FPGA-based architectures. In this paper, an application of balanced functional decomposition in other fields of modern engineering is presented. The experimental results demonstrate that a method of synthesis based on functional decomposition can help in implementing sequential machines using flip-flops or ROM memory. It also can be efficiently used as a method of multilevel logic synthesis for VLSI technology.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125161004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An implementation of an embedded microprocessor core with support for executing byte compiled Java code","authors":"Øyvind Strøm, E. Aas","doi":"10.1109/DSD.2001.952346","DOIUrl":"https://doi.org/10.1109/DSD.2001.952346","url":null,"abstract":"This paper presents and implementation of a novel microprocessor architecture for executing byte compiled Java programs directly in hardware. The processor features two programming models, a Java model and a RISC model. The entities share a common data path and may operate independently although not in parallel. This combination facilities access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities. Our processor targets medium to small embedded applications where performance in the sense of throughput is not the primary design objective, but rather the ability to execute Java code on a processor core with small die size and acceptable power consumption characteristics.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115359971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Economakos, S. Stergiou, G. Papakonstantinou, Vassilios Zoukos
{"title":"A multi-lingual synthesis and verification environment","authors":"G. Economakos, S. Stergiou, G. Papakonstantinou, Vassilios Zoukos","doi":"10.1109/DSD.2001.952111","DOIUrl":"https://doi.org/10.1109/DSD.2001.952111","url":null,"abstract":"The adoption of hardware description languages as a design specification formalism, in the electronic design automation industry, has reached acceptance during the last years. This effort has been mainly supported by the VHDL and Verilog standardization activities, which are now offering a common formalism among different tool vendors, as well as novel ideas like the SystemCC++ class library, which promises hardware modeling using C++ syntax and a higher level of specification abstraction. The broad range of modern description language spectrum, supports efficient language based synthesis processes, starting at even higher abstraction levels. This paper presents a language based design environment, which combines synthesis and formal verification tasks, using an advanced compiler generator and based on language transformations. This combination, presenting low complexity, offers more power to language based synthesis and design management and can be used to find errors and better understand issues of behavioral modeling.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116280808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interconnect-driven short-circuit power modeling","authors":"D. Eckerbert, P. Larsson-Edefors","doi":"10.1109/DSD.2001.952353","DOIUrl":"https://doi.org/10.1109/DSD.2001.952353","url":null,"abstract":"Early and accurate power estimation has become very important to meet the power budget in modern electronics design. In order to achieve early figures on power consumption, functional units have been modeled as black boxes and their respective power consumption has been modeled as a function of signal activity in inputs and outputs. Interconnects, and the associated load capacitances, are accounted for by simply adding the switching power consumption of the interconnect to the estimated power consumption of the functional unit driving the interconnect. Thus, the effects of load capacitance on short-circuit power in the functional units are not considered. The purpose of the present paper is two-fold: first, we put some focus on the review the effects that load capacitance has on short-circuit power. Secondly, we present two methods for interconnect-driven estimation of short-circuit power in state-of-the-art electronics design.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116402562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A multiple context reconfigurable functional unit","authors":"Michael C. Miller, D. Tabak","doi":"10.1109/DSD.2001.952364","DOIUrl":"https://doi.org/10.1109/DSD.2001.952364","url":null,"abstract":"A design for a reconfigurable functional unit, based on dynamically programmable gate arrays, is proposed. The design provides multiple concurrent configuration contexts for the purpose of supporting multiple execution streams. A discussion of the impact of the reconfigurable functional unit on each processor pipeline stage is presented. The proposed design is simulated and the system performance is compared to other designs.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"36 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129586576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}