{"title":"一个多上下文可重构的功能单元","authors":"Michael C. Miller, D. Tabak","doi":"10.1109/DSD.2001.952364","DOIUrl":null,"url":null,"abstract":"A design for a reconfigurable functional unit, based on dynamically programmable gate arrays, is proposed. The design provides multiple concurrent configuration contexts for the purpose of supporting multiple execution streams. A discussion of the impact of the reconfigurable functional unit on each processor pipeline stage is presented. The proposed design is simulated and the system performance is compared to other designs.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"36 9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A multiple context reconfigurable functional unit\",\"authors\":\"Michael C. Miller, D. Tabak\",\"doi\":\"10.1109/DSD.2001.952364\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A design for a reconfigurable functional unit, based on dynamically programmable gate arrays, is proposed. The design provides multiple concurrent configuration contexts for the purpose of supporting multiple execution streams. A discussion of the impact of the reconfigurable functional unit on each processor pipeline stage is presented. The proposed design is simulated and the system performance is compared to other designs.\",\"PeriodicalId\":285358,\"journal\":{\"name\":\"Proceedings Euromicro Symposium on Digital Systems Design\",\"volume\":\"36 9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-09-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Euromicro Symposium on Digital Systems Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DSD.2001.952364\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Euromicro Symposium on Digital Systems Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSD.2001.952364","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A design for a reconfigurable functional unit, based on dynamically programmable gate arrays, is proposed. The design provides multiple concurrent configuration contexts for the purpose of supporting multiple execution streams. A discussion of the impact of the reconfigurable functional unit on each processor pipeline stage is presented. The proposed design is simulated and the system performance is compared to other designs.
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