Test generation and fault simulation methods on the basis of cubic algebra for digital devices

Abstract

Models and methods of digital circuit analysis for test generation and fault simulation are offered. The two-frame cubic algebra for compact description of sequential primitive element (here and further, primitive) in the form of cubic coverings is used. It is used for digital circuit designing, fault simulation and fault-free simulation as well. Problems of digital circuit testing are formulated as linear equations. The described cubic fault simulation method allows to propagate primitive fault lists from its inputs to outputs; to generate analytical equations for deductive fault simulation of digital circuit at gate, functional and algorithmic description levels; to build comparative and interpretative fault simulators for digital circuit. The fault list cubic coverings (FLCC), which allow to create single sensitization paths, are proposed. The test generation method for single stuck-at fault (SSF) detection with usage of FLCC is developed.