Timing driven wiring on an advanced microprocessor

Abstract

The effect of wire delay within critical timing paths is becoming an increasing problem. By comparing the large improvement of transistor performance, due to shrinking L/sub eff/ or new technology such as silicon on insulator, versus the smaller improvements of wire delay, such as copper wires and better dielectrics, it can be seen that the wiring within an advanced microprocessor will become a more dominant portion of the critical paths. In deep sub-micron designs it is crucial to analyze and improve any wire dominated paths while assuming that the transistor delay continues to improve. This paper describes wire related improvements, such as an algorithmic wiring approach, wire bending and clock skew reduction that is used in the timing convergence of an advanced PowerPC microprocessor. The impact of wiring improvements is evaluated on the timing, clocking and wireability of the microprocessor.