Synchronizing a high-speed SIMD processor array

A synchronization method for a high speed scalable SIMD (Single instruction stream Multiple Data stream) processor array is presented. The method is developed for an architecture using distributed clocking and hierarchical SIMD control. In such an architecture, scalability is radically enhanced by an array-size independent (local) clock skew. This paper focuses on the instruction start synchronization problem inherent in a processor array when using the SIMD node of control and distributed clocking. It is shown how this can be solved in hardware, and bounds on the tolerable skew using this method are presented.