Proceedings Euromicro Symposium on Digital Systems Design最新文献_第3页

Evaluation of temporal formulas based on "checking by spheres" 基于“球核”的时间公式评价

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952267

Wiktor B. Daszczuk

引用次数: 10

Dynamic branch prediction using neural networks 基于神经网络的动态分支预测

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952279

G. Steven, Rubén Anguera, C. Egan, F. Steven, L. Vintan

引用次数: 24

Self-testing of user-programmed FPGAs based on the concept of linear segments 基于线性分段概念的用户编程fpga自测试

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952287

P. Tomaszewicz, M. Rawski

引用次数: 0

A wireless interconnection network for parallel processing 一种用于并行处理的无线互连网络

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952342

Jacek Marczynski, D. Tabak

引用次数: 4

A MIMD-based multi threaded real-time processor for pattern recognition 一种基于mimd的多线程实时模式识别处理器

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952335

F. Lesser, J. Cuveland, V. Lindenstruth, C. Reichling, R. Schneider, M. Schulz

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引用次数: 2

Reconfigurable computing: a new business model-and its impact on SoC design 可重构计算:一种新的商业模式及其对SoC设计的影响

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952125

R. Hartenstein

{"title":"Reconfigurable computing: a new business model-and its impact on SoC design","authors":"R. Hartenstein","doi":"10.1109/DSD.2001.952125","DOIUrl":"https://doi.org/10.1109/DSD.2001.952125","url":null,"abstract":"Making gate arrays obsolete, FPGAs are successfully proceeding from niche to mainstream. Like microprocessor usage, FPGA application is RAM-based, but by structural programming (also called \"(re)configuration\") instead of procedural programming. Now both, host and accelerator are RAM-based and as such also available on the same chip: a new approach to SoC design. Now also accelerator definition may be-at least partly-conveyed from vendor site to customer site. A new business model is needed. But this paradigm switch is still ignored: FPGAs do not repeat the RAM-based success story of the software industry. There is not yet a configware industry, since mapping applications onto FPGAs mainly uses hardware syntheses method. From a decade of world-wide research on Reconfigurable Computing another breed of reconfigurable platforms is an emerging future competitor to FPGAs. Supporting roughly single bit wide configurable logic blocks (CLBs) the mapping tools are mainly based on gate level methods-similar to CAD for hardware logic. In contrast to this fine-grained arrays of coarse-grained reconfigurable datapath units (rDPUs) with drastically reduced reconfigurability overhead: to directly configure high level parallelism. But the \"von Neumann\" paradigm does not support soft datapaths because \"instruction fetch\" is not done at run time, and, since most reconfigurable computing arrays do not run parallel processes, but multiple pipe networks instead.","PeriodicalId":285358,"journal":{"name":"Proceedings Euromicro Symposium on Digital Systems Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115202307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

On the use of mutations in Boolean minimization 关于布尔最小化中突变的使用

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952308

P. Fiser, J. Hlavicka

引用次数: 13

Evaluation of delay fault testability of LUT functions for improved efficiency of FPGA testing LUT函数延迟故障可测性评估，提高FPGA测试效率

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952312

A. Krasniewski

引用次数: 5

A design methodology for high performance ICs: wireless broadband radio baseband case study 高性能集成电路的设计方法:无线宽带无线电基带案例研究

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952112

V. Aue, J. Kneip, Matthias Weiss, M. Bolle, G. Fettweis

引用次数: 3

Traffic scheduling coprocessor with schedulability analysis capability 具有可调度性分析功能的交通调度协处理器

Proceedings Euromicro Symposium on Digital Systems Design Pub Date : 2001-09-04 DOI: 10.1109/DSD.2001.952254

E. Martins, J. Fonseca

引用次数: 2