Self-testing of user-programmed FPGAs based on the concept of linear segments

Abstract

A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of logic cones and linear segments. Linear segments that satisfy single-generator compatibility requirement can be combinationally-exhaustively tested in parallel and are merged into a test group. The number of test groups corresponds to the number of test sessions. A tool has been developed to implement the proposed algorithm of computing logic cones and linear segments. The presented experimental results are used to develop heuristic rules that control the computing process.