An assessment of FPGA suitability for implementation of real-time motion estimation

Motion estimation is very computational demanding operation during video compression process, thus special hardware architectures are required to achieve real-time compression performance. Advantages in increasing complexity, density and speed of programmable logic devices will soon allow us to implement this kind of application specific processors within one programmable chip. This paper evaluates the performance of Block Matching hardware architectures implemented in Xilinx FPGA. Systolic arrays for Full Search algorithm inferred by Komarek and Pirsch (1989) have been implemented and evaluated by achieved clock rate and number of occupied FPGA resources. Results show that with 2D type systolic arrays it is possible to achieve real-time performance of motion estimation for CIF images even with moderate capacity (250 k gates) FPGA chip.