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Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium最新文献

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Testability of one dimensional ILAs under multiple faults 一维集成电路在多重故障下的可测试性
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI: 10.1109/VTEST.1993.313327
M. Gala, K. Watson, D. Ross
{"title":"Testability of one dimensional ILAs under multiple faults","authors":"M. Gala, K. Watson, D. Ross","doi":"10.1109/VTEST.1993.313327","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313327","url":null,"abstract":"Testing of one dimensional unilateral iterative logic arrays (ILAs) of combinational cells under multiple faults is discussed. It has been shown that it is possible to generate a test set for ILAs with primary outputs under multiple faults. Some ILAs have a constant number of test vectors independent of the size of the array. These types of arrays are called C-testable arrays. Present work proves that all useful one dimensional unilateral ILAs with only boundary outputs are not C-testable under multiple faults.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122250159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Input and output encoding techniques for on-line error detection in combinational logic circuits 组合逻辑电路在线错误检测的输入输出编码技术
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI: 10.1109/VTEST.1993.313309
F. Busaba, P. Lala
{"title":"Input and output encoding techniques for on-line error detection in combinational logic circuits","authors":"F. Busaba, P. Lala","doi":"10.1109/VTEST.1993.313309","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313309","url":null,"abstract":"Presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit errors at the output. An input encoding algorithm and an output encoding algorithm that ensure that every fault at the input will either produce single bit error or unidirectional multibit errors at the output are proposed. If there are no input faults which produce bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way the circuit is implemented. The proposed techniques have been applied to MCNC benchmark circuits and the overhead is estimated.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122725527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Signal probability calculations using partial functional manipulation 使用部分函数操作的信号概率计算
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI: 10.1109/VTEST.1993.313324
Ravishankar Kodavarti, D. Ross
{"title":"Signal probability calculations using partial functional manipulation","authors":"Ravishankar Kodavarti, D. Ross","doi":"10.1109/VTEST.1993.313324","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313324","url":null,"abstract":"Signal probability calculations are necessary to determine the random pattern testability of logic circuits. Determination of random pattern testability is necessary for considering the use of weighted or unweighted linear feedback shift registers (LFSRs) as an appropriate testing method. This paper presents an algorithm to accurately and efficiently (both in space and time) calculate signal probabilities (sometimes called syndrome analysis) within digital logic networks. It has the advantage that it uses a new method for signal probability calculations which is typically both fast and accurate, and which has already efficiently produced results for all the ISCAS combinational circuits.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"117 37","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120820601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Time and space correlated errors in signature analysis 特征码分析中的时空相关误差
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI: 10.1109/VTEST.1993.313357
G. Edirisooriya, S. Edirisooriya, John P. Robinson
{"title":"Time and space correlated errors in signature analysis","authors":"G. Edirisooriya, S. Edirisooriya, John P. Robinson","doi":"10.1109/VTEST.1993.313357","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313357","url":null,"abstract":"A new error model that considers both space and time correlation is proposed. An exact closed form expression for aliasing probability is obtained for an arbitrary test length for a large class of signature registers. The authors identify the minimum register structure that falls into this class.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"250 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123344875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Combinational circuit ATPG using binary decision diagrams ATPG组合电路使用二进制决策图
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI: 10.1109/VTEST.1993.313354
S. Srinivasan, G. Swaminathan, J. Aylor, M. R. Mercer
{"title":"Combinational circuit ATPG using binary decision diagrams","authors":"S. Srinivasan, G. Swaminathan, J. Aylor, M. R. Mercer","doi":"10.1109/VTEST.1993.313354","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313354","url":null,"abstract":"The increasing size and complexity of current VLSI circuits has brought testing and design for testability into the mainstream of the design process. A significant amount of research has been done in the area of gate-level combinational ATPG using the stuck-at-fault model. The problem has been shown to be NP-complete and most of the current research attempts to find efficient ways to generate tests for hard faults in a reasonable amount of time on the average. Hence, there remains a lot of interest in the testing world for efficient techniques to do combinational ATPG. Use of ordered binary decision diagrams (OBDDs) for function representation has provided significant impetus to algebraic CAD techniques. This paper presents techniques for gate-level ATPG using OBDDs.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122938253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
ECC design of a custom DRAM storage unit 设计一种定制的ECC DRAM存储单元
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI: 10.1109/VTEST.1993.313329
J. Peter
{"title":"ECC design of a custom DRAM storage unit","authors":"J. Peter","doi":"10.1109/VTEST.1993.313329","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313329","url":null,"abstract":"The architecture and ECC (error correction code) implementation of a custom storage unit built with 4 Mb DRAMs packaged on 4 MB SIMM (single in line module) and controlled with a CMOS 1 micron ASIC chips set will be described. The upgrade with 16 Mb DRAMs chips packaged on 16 MB SIMM is also supported. The storage unit is designed to interface with an INTEL i486 microprocessor running at 25 MHz and to provide an optimum correction capability of the ECC based on expected DRAMs chip failures mechanisms. This storage unit is used in the 3746 model 900 Communication Controller announced by IBM. The maximum DRAM space supported is 50 SIMMs.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131595337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A model for testing reliable VLSI routing architectures 一个测试可靠VLSI路由架构的模型
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI: 10.1109/VTEST.1993.313373
C. Stivaros
{"title":"A model for testing reliable VLSI routing architectures","authors":"C. Stivaros","doi":"10.1109/VTEST.1993.313373","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313373","url":null,"abstract":"Presents a model for testing the reliability of VLSI interconnection topologies. It is assumed that terminals on an electronic board may fail to operate independently and with manufacturer-supplied probabilities. The authors are concerned with the ability of the operating terminals to communicate in order to carry out their tasks. The two schemes examined are the channel and match-box routing topologies which are translated to their underlying probabilistic graphs as an illustration of the applicability of combinatorial optimization techniques. Their optimality is tested under all possible failure vectors.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123542681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Testability analysis based on structural and behavioral information 基于结构和行为信息的可测试性分析
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI: 10.1109/VTEST.1993.313335
Jaushin Lee, J. Patel
{"title":"Testability analysis based on structural and behavioral information","authors":"Jaushin Lee, J. Patel","doi":"10.1109/VTEST.1993.313335","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313335","url":null,"abstract":"When VLSI circuits such as microprocessors are designed hierarchically, testability issues have to be considered simultaneously with functional specifications to reduce the testing complexity early in the design phase. Accurate testability measures are required to indicate the hard-to-test areas and can be used as a guidance for ATPG. This paper presents a new testability analysis technique operating at a high level using both circuit structural information and assembly-level instruction behavioral information. This testability analysis targets at the popular functional test generation and a modern high level ATPG methodology published in recent literature. The experimental results of testability measures as well as high level ATPG are presented to verify the effectiveness.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125880477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Physical design for testability for bridges in CMOS circuits CMOS电路中电桥可测试性的物理设计
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI: 10.1109/VTEST.1993.313361
F. Ferguson
{"title":"Physical design for testability for bridges in CMOS circuits","authors":"F. Ferguson","doi":"10.1109/VTEST.1993.313361","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313361","url":null,"abstract":"Present research in design for testability has largely been confined to the logic level. This paper presents directions for research in design for testability at the layout or physical design level. These are illustrated for bridge faults in circuits consisting of CMOS standard cells.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128231491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Minimal hardware multiple signature analysis for BIST 最小的硬件多重签名分析的BIST
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium Pub Date : 1993-04-06 DOI: 10.1109/VTEST.1993.313314
Yuejian Wu, A. Ivanov
{"title":"Minimal hardware multiple signature analysis for BIST","authors":"Yuejian Wu, A. Ivanov","doi":"10.1109/VTEST.1993.313314","DOIUrl":"https://doi.org/10.1109/VTEST.1993.313314","url":null,"abstract":"Proposes a new BIST multiple intermediate signature analysis scheme which checks n signatures against a single reference. Therefore, the circuitry for checking n signatures is essentially the same as that for checking one signature. The scheme is based on a manipulation of the CUT's fault-free output sequence. No circuit modification is required. The cost for implementing the scheme is a small nonrecurring CPU time expenditure in the design phase. In return, the scheme yields significant recurring silicon area savings, and reduced aliasing.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128653845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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