{"title":"一个测试可靠VLSI路由架构的模型","authors":"C. Stivaros","doi":"10.1109/VTEST.1993.313373","DOIUrl":null,"url":null,"abstract":"Presents a model for testing the reliability of VLSI interconnection topologies. It is assumed that terminals on an electronic board may fail to operate independently and with manufacturer-supplied probabilities. The authors are concerned with the ability of the operating terminals to communicate in order to carry out their tasks. The two schemes examined are the channel and match-box routing topologies which are translated to their underlying probabilistic graphs as an illustration of the applicability of combinatorial optimization techniques. Their optimality is tested under all possible failure vectors.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A model for testing reliable VLSI routing architectures\",\"authors\":\"C. Stivaros\",\"doi\":\"10.1109/VTEST.1993.313373\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Presents a model for testing the reliability of VLSI interconnection topologies. It is assumed that terminals on an electronic board may fail to operate independently and with manufacturer-supplied probabilities. The authors are concerned with the ability of the operating terminals to communicate in order to carry out their tasks. The two schemes examined are the channel and match-box routing topologies which are translated to their underlying probabilistic graphs as an illustration of the applicability of combinatorial optimization techniques. Their optimality is tested under all possible failure vectors.<<ETX>>\",\"PeriodicalId\":283218,\"journal\":{\"name\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1993.313373\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1993.313373","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A model for testing reliable VLSI routing architectures
Presents a model for testing the reliability of VLSI interconnection topologies. It is assumed that terminals on an electronic board may fail to operate independently and with manufacturer-supplied probabilities. The authors are concerned with the ability of the operating terminals to communicate in order to carry out their tasks. The two schemes examined are the channel and match-box routing topologies which are translated to their underlying probabilistic graphs as an illustration of the applicability of combinatorial optimization techniques. Their optimality is tested under all possible failure vectors.<>
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