{"title":"设计一种定制的ECC DRAM存储单元","authors":"J. Peter","doi":"10.1109/VTEST.1993.313329","DOIUrl":null,"url":null,"abstract":"The architecture and ECC (error correction code) implementation of a custom storage unit built with 4 Mb DRAMs packaged on 4 MB SIMM (single in line module) and controlled with a CMOS 1 micron ASIC chips set will be described. The upgrade with 16 Mb DRAMs chips packaged on 16 MB SIMM is also supported. The storage unit is designed to interface with an INTEL i486 microprocessor running at 25 MHz and to provide an optimum correction capability of the ECC based on expected DRAMs chip failures mechanisms. This storage unit is used in the 3746 model 900 Communication Controller announced by IBM. The maximum DRAM space supported is 50 SIMMs.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"ECC design of a custom DRAM storage unit\",\"authors\":\"J. Peter\",\"doi\":\"10.1109/VTEST.1993.313329\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The architecture and ECC (error correction code) implementation of a custom storage unit built with 4 Mb DRAMs packaged on 4 MB SIMM (single in line module) and controlled with a CMOS 1 micron ASIC chips set will be described. The upgrade with 16 Mb DRAMs chips packaged on 16 MB SIMM is also supported. The storage unit is designed to interface with an INTEL i486 microprocessor running at 25 MHz and to provide an optimum correction capability of the ECC based on expected DRAMs chip failures mechanisms. This storage unit is used in the 3746 model 900 Communication Controller announced by IBM. The maximum DRAM space supported is 50 SIMMs.<<ETX>>\",\"PeriodicalId\":283218,\"journal\":{\"name\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1993.313329\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1993.313329","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The architecture and ECC (error correction code) implementation of a custom storage unit built with 4 Mb DRAMs packaged on 4 MB SIMM (single in line module) and controlled with a CMOS 1 micron ASIC chips set will be described. The upgrade with 16 Mb DRAMs chips packaged on 16 MB SIMM is also supported. The storage unit is designed to interface with an INTEL i486 microprocessor running at 25 MHz and to provide an optimum correction capability of the ECC based on expected DRAMs chip failures mechanisms. This storage unit is used in the 3746 model 900 Communication Controller announced by IBM. The maximum DRAM space supported is 50 SIMMs.<>
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