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2016 International SoC Design Conference (ISOCC)最新文献

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Cell-based delay locked loop compiler 基于单元格的延迟锁定循环编译器
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799748
P. Huang, Shi-Yu Huang
{"title":"Cell-based delay locked loop compiler","authors":"P. Huang, Shi-Yu Huang","doi":"10.1109/ISOCC.2016.7799748","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799748","url":null,"abstract":"Digital Delay-Locked Loops (DLLs) have been widely used in today's ICs for all kinds of timing control. Even though a digital DLL circuit is much easier to design than its analog counterparts, our prior experience shows that weeks of efforts, if not months, could still be wasted in order to find a process resilient configuration for a specific DLL requirement. Thus, we propose in this work a cell-based DLL architecture and its compiler. According to a user's demand, our DLL compiler can generate a cell-based DLL circuit in just minutes, it can support easy process migration, and thereby saving a large amount of human efforts spent in tuning DLL designs for different manufacturing processes. Transistor-level simulation has been used to validate its ability in a 0.18 CMOS process and a 90nm CMOS process. It can support input clock frequency up to 1GHz in 0.18 μm, and 1.25GHz in 90nm.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125635576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
μPnP-WAN: Wide area plug and play sensing and actuation with LoRa μPnP-WAN:具有LoRa的广域即插即用传感和驱动
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799869
F. Yang, G. Ramachandran, Piers W. Lawrence, Sam Michiels, W. Joosen, D. Hughes
{"title":"μPnP-WAN: Wide area plug and play sensing and actuation with LoRa","authors":"F. Yang, G. Ramachandran, Piers W. Lawrence, Sam Michiels, W. Joosen, D. Hughes","doi":"10.1109/ISOCC.2016.7799869","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799869","url":null,"abstract":"The Internet of Things (IoT) is being applied in a wide variety of applications, which demand a range of networking support, including long range technologies. Unfortunately, emerging long range IoT platforms are difficult to deploy and configure for end-users who are not IoT specialists. This paper addresses this problem by introducing μPnP-WAN, which combines the ease of use of the μPnP peripheral system, with the long range LoRa network to realize the first true plug- and-play solution for long-range sensing and actuation. μPnP-WAN can achieve a range of up to 3.5 kilometers in ad-hoc suburban deployments and multi-year battery lifetime.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125646696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Moving objects detection using classifying object proposals for driver assistance system 基于物体分类的驾驶员辅助系统运动物体检测方案
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799839
Kunyao Chen, Subarna Tripathi, Youngbae Hwang, Truong Q. Nguyen
{"title":"Moving objects detection using classifying object proposals for driver assistance system","authors":"Kunyao Chen, Subarna Tripathi, Youngbae Hwang, Truong Q. Nguyen","doi":"10.1109/ISOCC.2016.7799839","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799839","url":null,"abstract":"We present a new framework for driver assistance system, detecting moving objects in the street scene. Our algorithm supports a wide range of objects including vehicles, cyclists, pedestrian etc. Based on candidate bounding boxes detected by object proposals, our classifier only responds to the objects truly moving, which is more practical for real applications. Using unified features of color, structure and motion information, our system runs in real time with 66% detection rate in CamVid dataset. In addition, our method can be implemented efficiently with pipelined function blocks.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132348257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system 用于10gb /s传输标签信号系统的敏感频率解调器方案
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799771
N. Koda, Kosuke Furuichi, H. Uemura, H. Inaba, K. Kishine
{"title":"Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system","authors":"N. Koda, Kosuke Furuichi, H. Uemura, H. Inaba, K. Kishine","doi":"10.1109/ISOCC.2016.7799771","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799771","url":null,"abstract":"In this paper, we propose a frequency demodulation circuit for realizing multiplex communication called a \"labeling signal system.\" The proposed circuit configuration consists of delay circuits and logic circuits. In this work, a frequency demodulator designed with discrete devices detects information with an FPGA. Compared with the conventional delay detection circuit, the proposed circuit successfully increased the voltage change in accordance with the frequency shift. We also confirm its operating characteristics and advantages from the experimental results.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127542985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-power multi-sensor system with normally-off sensing technology for IoT applications 低功耗多传感器系统，具有物联网应用的常关传感技术
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799854
M. Hayashikoshi, H. Noda, H. Kawai, H. Kondo
{"title":"Low-power multi-sensor system with normally-off sensing technology for IoT applications","authors":"M. Hayashikoshi, H. Noda, H. Kawai, H. Kondo","doi":"10.1109/ISOCC.2016.7799854","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799854","url":null,"abstract":"We propose the low-power multi-sensor system with normally-off sensing technology for IoT applications, which achieves almost zero standby power at the no-operation modes. A hierarchical power management scheme with activity localization can be reduced the number of transitions between power-on and power-off modes with re-scheduling and bundling task procedures. We also propose autonomously standby mode transition control by selecting optimum standby mode of microcontrollers, reducing total power consumption in the multisensor network. The prototyping evaluation boards with sensors are developed and demonstrated, observing 91% power reductions by adopting the proposed power gating and autonomously standby mode transition control.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115107118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A design of dual-band smart tag 一种双频段智能标签的设计
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799699
Jinho Kim, Yong Moon
{"title":"A design of dual-band smart tag","authors":"Jinho Kim, Yong Moon","doi":"10.1109/ISOCC.2016.7799699","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799699","url":null,"abstract":"The dual-band smart tag is designed and is fabricated using a 0.18 μm 1-Poly 4-Metal CMOS Process, and the area is 5mm × 5mm. The dual-band smart tag can recognize and demodulate the frequency bands of both UHF band (868 ~ 956 MHz) and HF band (13.56 MHz). The Digital block for verification is programmed in Arduino Uno board. Consequently, the dual-band smart tag communicates between the HF/UHF reader and the tag.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123670346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware implementation of aggregated channel features for ADAS ADAS聚合通道特性的硬件实现
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799844
Hohyon Song, Bosun Jeong, Hyunkyu Choi, Taeho Cho, Hweihn Chung
{"title":"Hardware implementation of aggregated channel features for ADAS","authors":"Hohyon Song, Bosun Jeong, Hyunkyu Choi, Taeho Cho, Hweihn Chung","doi":"10.1109/ISOCC.2016.7799844","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799844","url":null,"abstract":"In this paper, we propose the hardware detector architecture implemented in the semiconductor level to achieve the higher speed and performance efficiently as pre-processor for ADAS vision system compared to the existing solution which is done by ECU side only or S/W implemented intently. Herein the architecture represents the higher speed as real time that we implement a hardware multi-scale pedestrian detector operating in real time (30fps on 640×480 images, full-search) and performance as ACF based for detection algorithm in a highly integrated manner. Its advanced ADAS algorithms deliver highly improved detection rate eventually. For the efficient method, we construct the image pyramid directly rather than using the approximate features at nearby scale for providing greater accuracy. To actualize it in an effective way, we design the detector separately as two parts - H/W part and S/W part. In other words, H/W part generates pyramid images and extracts features then does classification. S/W part does clustering from the H/W classification result using NMS. As a simulation result, the performance is 18%@10-1FPPI in the INRIA DB. According to well-defined system partitioning, it offers faster calculation and securing higher detection rate.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115398059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Implementation of Low complexity inter prediction for IoT systems 物联网系统低复杂度相互预测的实现
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799807
Jaehyuk So, J. Mun, Kyungmook Oh, Jaeseok Kim
{"title":"Implementation of Low complexity inter prediction for IoT systems","authors":"Jaehyuk So, J. Mun, Kyungmook Oh, Jaeseok Kim","doi":"10.1109/ISOCC.2016.7799807","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799807","url":null,"abstract":"In this paper, we presents efficient hardware design of inter picture prediction in the slim - high efficient video coding (HEVC). Compared with fully implemented HM10.0, our compression performance of inter prediction hardware block is decreased due to simplification. However our target is Real-time Encoder suitable for IoT, so our inter prediction block is small and fast. Also the verification of the inter prediction design is conducted using the ZYNQ and Virtex7.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"329 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122832543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new approach to binarizing neural networks 神经网络二值化的新方法
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799741
J. Seo, Joonsang Yu, Jongeun Lee, Kiyoung Choi
{"title":"A new approach to binarizing neural networks","authors":"J. Seo, Joonsang Yu, Jongeun Lee, Kiyoung Choi","doi":"10.1109/ISOCC.2016.7799741","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799741","url":null,"abstract":"As deep neural networks grow larger, they suffer from a huge number of weights, and thus reducing the overhead of handling those weights becomes one of key challenges nowadays. This paper presents a new approach to binarizing neural networks, where the weights are pruned and forced to take degenerate binary values. Experimental results show that the proposed approach achieves significant reductions in computation and power consumption at the cost of a slight accuracy loss.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124901119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design of an area-efficient hardware filter for embedded system 嵌入式系统中面积高效硬件滤波器的设计
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799871
Ji Kwang Kim, Oh Seong Gwon, Seung Eun Lee
{"title":"Design of an area-efficient hardware filter for embedded system","authors":"Ji Kwang Kim, Oh Seong Gwon, Seung Eun Lee","doi":"10.1109/ISOCC.2016.7799871","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799871","url":null,"abstract":"In this paper, we propose an area-efficient hardware accelerated filter for embedded system. In order to minimize the area of hardware filter, the proposed filter architecture has a single multiplier. The filter operates by reusing the multiplier. In addition, we optimize the quantization bit length by analyzing the relationship between area and preciseness according to the quantization bit length. We verify the performance of the proposed filter by measuring frequency response in verification environment.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129562970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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