Design of an area-efficient hardware filter for embedded system

Abstract

In this paper, we propose an area-efficient hardware accelerated filter for embedded system. In order to minimize the area of hardware filter, the proposed filter architecture has a single multiplier. The filter operates by reusing the multiplier. In addition, we optimize the quantization bit length by analyzing the relationship between area and preciseness according to the quantization bit length. We verify the performance of the proposed filter by measuring frequency response in verification environment.