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2016 International SoC Design Conference (ISOCC)最新文献

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Development of an IoT-based visitor detection system 基于物联网的访客检测系统的开发
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799787
Hyoung-Ro Lee, Chi-Ho Lin, Won-Jong Kim
{"title":"Development of an IoT-based visitor detection system","authors":"Hyoung-Ro Lee, Chi-Ho Lin, Won-Jong Kim","doi":"10.1109/ISOCC.2016.7799787","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799787","url":null,"abstract":"In this paper, we proposed an IoT-based visitor detection system. It uses an IR sensor to detect human body and two ultrasonic sensors to locate visitor servo motor under the position. When a visitor is detected it drives camera module to locate the visitor. Recoded video and sensor data are stored in the Database. Saved data can see via the PC and Smart device. We developed the system using Raspberry Pi2 and sensor modules to verify the concept. It can track the visitor moving route and minimize the blind spots of the camera. And sensor data and recoded video are checked internet possible all remote location.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127534210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A CMOS buck converter with PFM / hysteretic mode 具有PFM /迟滞模式的CMOS降压变换器
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799820
Taeheon Lee, Jonggu Kim, K. Yoon
{"title":"A CMOS buck converter with PFM / hysteretic mode","authors":"Taeheon Lee, Jonggu Kim, K. Yoon","doi":"10.1109/ISOCC.2016.7799820","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799820","url":null,"abstract":"This paper proposes design of a CMOS DC-DC buck converter with Fixed Hysteretic mode and PFM(Pulse Frequency Modulation) mode. The inherent problems of a slow transient time from heavy load to light load that the conventional Dual DC-DC buck converters with PWM/PFM mode has faced have been resolved by using the proposed DC-DC buck converter which employed Hysteretic mode in heavy load. It improves transient time in load regulation. This also can maintain range of wide load current, advantage of Dual mode buck converter. The proposed Dual Buck Converter is fabricated in 180nm CMOS 1-poly 6-metal process and occupies a core effective area of 1.35 mm2. Measurement environment are input voltage range of 2.7~3.3V, output voltage 1.2V and load current range from 10mA to 500mA. And measurement result shows that the maximum efficiency is 90% and ripple voltage is less 1.32mV.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127948901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dehazing in color filter array domain 彩色滤光器阵列域的去雾
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799846
Yeejin Lee, Truong Q. Nguyen, Changyoung Han
{"title":"Dehazing in color filter array domain","authors":"Yeejin Lee, Truong Q. Nguyen, Changyoung Han","doi":"10.1109/ISOCC.2016.7799846","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799846","url":null,"abstract":"This paper introduces an alternative image processing pipeline for efficiently implementing dehazing algorithms. In the proposed pipeline framework, demosaicking is performed after dehazing process and transmission is estimated in a color filter array plane itself. The proposed method reduces implementation complexity and suppresses demosaicking artifacts amplification. Experimental results verify that the proposed pipeline framework requires less memory resources and reduces computational complexity while preserving visual quality.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117241756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS 10-bit SAR ADC with threshold configuring comparator for 5 MSBs 一个CMOS 10位SAR ADC，具有5个msb的阈值配置比较器
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799774
Sang Heon Lee, Seong Jae Hyeon, Kim Jong Gu, K. Yoon
{"title":"A CMOS 10-bit SAR ADC with threshold configuring comparator for 5 MSBs","authors":"Sang Heon Lee, Seong Jae Hyeon, Kim Jong Gu, K. Yoon","doi":"10.1109/ISOCC.2016.7799774","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799774","url":null,"abstract":"This paper describes a CMOS 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) using TCC(Threshold Configuring Comparator) for the 5 MSBs. This architecture enables SAR to simplify C-DAC and reduce power consumption. The proposed SAR ADC is fabricated in 180nm CMOS and occupies a core area of 750um × 700um. It consumes 53uW and achieves an ENOB of 9.7 bits at sampling frequency 10MS/s, power supply of 1.8V, and reference of 1.2 V. The Figure of Merit (FOM) is simulated to be 6.37fJ/step.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125980177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cryptographie coprocessor design for IoT sensor nodes 物联网传感器节点的加密协处理器设计
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799761
Weizhen Wang, Jun Han, Zhicheng Xie, Shan Huang, Xiaoyang Zeng
{"title":"Cryptographie coprocessor design for IoT sensor nodes","authors":"Weizhen Wang, Jun Han, Zhicheng Xie, Shan Huang, Xiaoyang Zeng","doi":"10.1109/ISOCC.2016.7799761","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799761","url":null,"abstract":"Together with the popularity of internet of things (IoT), the information security in IoT is becoming an urgent issue. In this paper, a cryptographic coprocessor is designed to provide security for IoT sensor nodes. This design incorporates the application-specific instruction set to support popular cryptography algorithms like advanced encryption standard (AES) and elliptic curve cryptography (ECC). The tailored instruction provides good flexibility, high energy efficiency and low latency. Local instruction and data ram is integrated into our coprocessor to reduce the instruction transfer between embedded processor and the coprocessor. Our work was synthesized under TSMC 65 nm technology. The measurement results show that our design consumes 32.7 uJ for each ECC point multiplication and 3 nJ for each AES encryption and decryption when working at 10 MHz.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130642628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Integrated circuits design using carbon nanotube field effect transistor 利用碳纳米管场效应晶体管设计集成电路
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799722
Yong-Bin Kim
{"title":"Integrated circuits design using carbon nanotube field effect transistor","authors":"Yong-Bin Kim","doi":"10.1109/ISOCC.2016.7799722","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799722","url":null,"abstract":"Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decaCNTFEdes. However, the bulk CMOS technology has approached the scaling limit due to the increased short-channel effects as technology scales down to 90 nm and below. Last about a decade witnessed a dramatic increase in nanotechnology research, especially the nano-electronics. These technologies vary in their maturity. Carbon nanotubes (CNTFETs) are at the forefront of these emerging technologies because of the unique mechanical and electronic properties. This paper discusses and reviews the feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"171 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134161259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability 一种低功耗，高速基于FinFET的6T SRAM单元，具有增强的写入能力和读取稳定性
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799802
Rahaprian Mudiarasan Premavathi, Q. Tong, K. Choi, Yunsik Lee
{"title":"A low power, high speed FinFET based 6T SRAM cell with enhanced write ability and read stability","authors":"Rahaprian Mudiarasan Premavathi, Q. Tong, K. Choi, Yunsik Lee","doi":"10.1109/ISOCC.2016.7799802","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799802","url":null,"abstract":"This paper presents a FinFET based 6T SRAM cell, with separate read access path and write path, designed by combining the advantages of conventional single ended 5T and the conventional 8T SRAM cells. The proposed SRAM cell achieves 70% and 55% of write performance improvement in terms of Power delay product (PDP) than 8T (also conventional 6T) and 5T SRAM cells respectively. Proposed cell achieves 78% of hold 1 and 40% of hold 0 static power reduction than the conventional 5T, 6T and 8T cells. The proposed cell is read SNM free and also achieves better hold SNM and write ability than 5T and 8T SRAM cells.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132729222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low-power 10-bit single-slope ADC using power gating and multi-clocks for CMOS image sensors 采用功率门控和多时钟的低功耗10位单斜率ADC，用于CMOS图像传感器
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799775
Byoung-Kwan Jeon, Seongkwan Hong, O. Kwon
{"title":"A low-power 10-bit single-slope ADC using power gating and multi-clocks for CMOS image sensors","authors":"Byoung-Kwan Jeon, Seongkwan Hong, O. Kwon","doi":"10.1109/ISOCC.2016.7799775","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799775","url":null,"abstract":"This paper proposes a low power 10-bit single-slope analog-to-digital converter (SS-ADC) for CMOS image sensors (CISs) with a column-parallel readout structure. The power consumption of the proposed SS-ADC is reduced by using a power gating scheme for the comparator and multi-clocks having different frequencies. The proposed SS-ADC was designed using a 0.13μm CIS process technology. The simulation results show that the power consumption of the proposed SS-ADC is 9.7 μW, which is 59.4 % less than that of the conventional SS-ADC.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133333234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Efficient and real-time stereo matching hardware architecture for high-resolution image 高分辨率图像的高效实时立体匹配硬件架构
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799783
Haengson Son, Seonyoung Lee, Kyoungwon Min
{"title":"Efficient and real-time stereo matching hardware architecture for high-resolution image","authors":"Haengson Son, Seonyoung Lee, Kyoungwon Min","doi":"10.1109/ISOCC.2016.7799783","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799783","url":null,"abstract":"In this paper, we propose an efficient and real-time stereo matching hardware architecture for a high resolution image. Disparity estimation algorithm must be operated at a real-time to be of practical use for applications such as an autonomous driving. However, they generally require large computational efforts and high memory capacities in the embedded processor-based systems. To solve this problem, we studied the real-time stereo matching hardware architecture and implemented in hardware system. Our architecture was implemented using Verilog HDL. Our circuit uses 95% LUT, 92% FF and 80% BRAM of Zynq XC7Z020 FPGA. Also, our hardware circuit can generate the depth data for the high-resolution images which receive from cameras without delays in the real time.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115254989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mapping table-based fisheye image correction for low computational complexity 基于映射表的低计算复杂度鱼眼图像校正
2016 International SoC Design Conference (ISOCC) Pub Date : 2016-10-01 DOI: 10.1109/ISOCC.2016.7799760
Y. Ahn, Suk-ju Kang
{"title":"Mapping table-based fisheye image correction for low computational complexity","authors":"Y. Ahn, Suk-ju Kang","doi":"10.1109/ISOCC.2016.7799760","DOIUrl":"https://doi.org/10.1109/ISOCC.2016.7799760","url":null,"abstract":"In this paper, we proposed a mapping table-based fisheye image correction to reduce computation time. Specifically, the proposed algorithm uses the field of view correction model and camera coordinate conversion when performing an image interpolation for generating an image with the target image size. The experimental results show that the proposed algorithm reduces the computation time up to 15.85% while improving perceptual image quality, compared with the benchmark algorithm.","PeriodicalId":278207,"journal":{"name":"2016 International SoC Design Conference (ISOCC)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116284930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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