Efficient and real-time stereo matching hardware architecture for high-resolution image

Abstract

In this paper, we propose an efficient and real-time stereo matching hardware architecture for a high resolution image. Disparity estimation algorithm must be operated at a real-time to be of practical use for applications such as an autonomous driving. However, they generally require large computational efforts and high memory capacities in the embedded processor-based systems. To solve this problem, we studied the real-time stereo matching hardware architecture and implemented in hardware system. Our architecture was implemented using Verilog HDL. Our circuit uses 95% LUT, 92% FF and 80% BRAM of Zynq XC7Z020 FPGA. Also, our hardware circuit can generate the depth data for the high-resolution images which receive from cameras without delays in the real time.