A CMOS buck converter with PFM / hysteretic mode

Taeheon Lee, Jonggu Kim, K. Yoon
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Abstract

This paper proposes design of a CMOS DC-DC buck converter with Fixed Hysteretic mode and PFM(Pulse Frequency Modulation) mode. The inherent problems of a slow transient time from heavy load to light load that the conventional Dual DC-DC buck converters with PWM/PFM mode has faced have been resolved by using the proposed DC-DC buck converter which employed Hysteretic mode in heavy load. It improves transient time in load regulation. This also can maintain range of wide load current, advantage of Dual mode buck converter. The proposed Dual Buck Converter is fabricated in 180nm CMOS 1-poly 6-metal process and occupies a core effective area of 1.35 mm2. Measurement environment are input voltage range of 2.7~3.3V, output voltage 1.2V and load current range from 10mA to 500mA. And measurement result shows that the maximum efficiency is 90% and ripple voltage is less 1.32mV.
具有PFM /迟滞模式的CMOS降压变换器
本文提出了一种具有固定滞回模式和脉冲调频模式的CMOS DC-DC降压变换器的设计。采用大负载滞回模式的DC-DC降压变换器,解决了传统PWM/PFM模式双DC-DC降压变换器从重负载到轻负载瞬态时间慢的固有问题。提高了负荷调节的暂态时间。这也可以保持宽负载电流范围,双模降压变换器的优点。所提出的双降压变换器采用180nm CMOS 1-聚6-金属工艺制造,核心有效面积为1.35 mm2。测量环境输入电压范围为2.7~3.3V,输出电压为1.2V,负载电流范围为10mA ~ 500mA。测试结果表明,该电路的最大效率为90%,纹波电压小于1.32mV。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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