Hardware implementation of aggregated channel features for ADAS

Abstract

In this paper, we propose the hardware detector architecture implemented in the semiconductor level to achieve the higher speed and performance efficiently as pre-processor for ADAS vision system compared to the existing solution which is done by ECU side only or S/W implemented intently. Herein the architecture represents the higher speed as real time that we implement a hardware multi-scale pedestrian detector operating in real time (30fps on 640×480 images, full-search) and performance as ACF based for detection algorithm in a highly integrated manner. Its advanced ADAS algorithms deliver highly improved detection rate eventually. For the efficient method, we construct the image pyramid directly rather than using the approximate features at nearby scale for providing greater accuracy. To actualize it in an effective way, we design the detector separately as two parts - H/W part and S/W part. In other words, H/W part generates pyramid images and extracts features then does classification. S/W part does clustering from the H/W classification result using NMS. As a simulation result, the performance is 18%@10-1FPPI in the INRIA DB. According to well-defined system partitioning, it offers faster calculation and securing higher detection rate.